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1. introduction this data sheet describes the functionality of the clrc632 integrated circuit (ic). it includes the functional and electrical speci?cations and from a system and hardware viewpoint gives detailed information on how to design-in the device. remark: the clrc632 supports all variants of the mifare mini, mifare 1k, mifare 4k and mifare ultralight rf identi?cation protocols. to aid readability throughout this data sheet, the mifare mini, mifare 1k, mifare 4k and mifare ultralight products and protocols have the generic name mifare. 2. general description the clrc632 is a member of a new family of highly integrated reader ics for contactless communication at 13.56 mhz. this family of reader ics provide: ? outstanding modulation and demodulation for passive contactless communication ? a wide range of methods and protocols ? a small, fully integrated package ? pin compatibility with the mfrc500, mfrc530, mfrc531 and slrc400 all protocol layers of the iso/iec 14443 a and iso/iec 14443 b communication standards are supported provided: ? additional components, such as the oscillator, power supply, coil etc. are correctly applied. ? standardized protocols, such as iso/iec 14443-4 and/or iso/iec 14443 b anticollision are correctly implemented using this nxp semiconductors device according to iso/iec 14443 b may infringe third party patent rights. the clrc632 supports contactless communication using mifare higher baud rates (see section 9.12 on page 40 ). the receiver module provides a robust and ef?cient demodulation/decoding circuitry implementation for compatible transponder signals (see section 9.10 on page 34 ). the digital module, manages the complete iso/iec 14443 standard framing and error detection (parity and crc). in addition, it supports the fast mifare security algorithm for authenticating the mifare products (see section 9.14 on page 42 ). clrc632 multiple protocol contactless reader ic (mifare/i-code1) rev. 3.5 10 november 2009 073935 product data sheet public
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 2 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) all layers of the i-code1 and iso/iec 15693 protocols are supported by the clrc632. the receiver module provides a robust and ef?cient demodulation/decoding circuitry implementation for i-code1 and iso/iec 15693 compatible transponder signals. the digital module handles i-code1 and iso/iec 15693 framing and error detection (crc). the internal transmitter module ( section 9.9 on page 31 ) can directly drive an antenna designed for a proximity operating distance up to 100 mm without any additional active circuitry. a parallel interface can be directly connected to any 8-bit microprocessor to ensure reader/terminal design ?exibility. in addition, serial peripheral interface (spi) compatibility is supported (see section 9.1.4 on page 9 ). 3. features 3.1 general n highly integrated analog circuitry for demodulating and decoding card/label response n buffered output drivers enable antenna connection using the minimum of external components n proximity operating distance up to 100 mm n supports both iso/iec 14443 a and iso/iec 14443 b standards n supports mifare dual-interface card ics and the mifare mini, mifare 1k, mifare 4k protocols n contactless communication at mifare higher baud rates (up to 424 kbd) n supports both i-code1 and iso/iec 15693 protocols n crypto1 and secure non-volatile internal key memory n pin-compatible with the mfrc500, mfrc530, mfrc531 and the slrc400 n parallel microprocessor interface with internal address latch and irq line n spi compatibility n flexible interrupt handling n automatic detection of parallel microprocessor interface type n 64-byte send and receive fifo buffer n hard reset with low power function n software controlled power-down mode n programmable timer n unique serial number n user programmable start-up con?guration n bit-oriented and byte oriented framing n independent power supply pins for analog, digital and transmitter modules n internal oscillator buffer optimized for low phase jitter enables 13.56 mhz quartz connection n clock frequency ?ltering n 3.3 v to 5 v operation for transmitter in short range and proximity applications n 3.3 v or 5 v operation for the digital module
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 3 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 4. applications n electronic payment systems n identi?cation systems n access control systems n subscriber services n banking systems n digital content systems 5. quick reference data 6. ordering information table 1. quick reference data symbol parameter conditions min typ max unit t amb ambient temperature - 40 - +150 c t stg storage temperature - 40 - +150 c v ddd digital supply voltage - 0.5 5 6 v v dda analog supply voltage - 0.5 5 6 v v dd(tvdd) tvdd supply voltage - 0.5 5 6 v | v i | input voltage (absolute value) on any digital pin to dvss - 0.5 - v ddd + 0.5 v on pin rx to avss - 0.5 - v dda + 0.5 v i li input leakage current - 1.0 - - 1.0 ma i dd(tvdd) tvdd supply current continuous wave - - 150 ma table 2. ordering information type number package name description version CLRC63201T/0fe so32 plastic small outline package; 32 leads; body width 7.5 mm sot287-1
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 4 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 7. block diagram fig 1. clrc632 block diagram 001aaj629 fifo control 64-byte fifo master key buffer cyrpto1 unit control register bank nwr nrd ncs ale a0 a1 a2 10 11 9 21 22 23 24 13 14 15 16 17 18 19 20 ad0 to ad7/d0 to d7 state machine clrc632 command register programmable timer interrupt control crc16/crc8 generation and check parallel/serial converter bit counter parity generation and check frame generation and check serial data switch bit decoding bit encoding 32 16-byte eeprom eeprom access control 32-bit pseudo random generator amplitude rating clock generation, filtering and distribution oscillator level shifters correlation and bit decoding reference voltage q-channel amplifier q-channel demodulator i-channel amplifier analog test multiplexer i-channel demodulator parallel interface control (including automatic interface detection and synchronisation) voltage monitor and power on detect dvdd rstpd q-clock generation transmitter control gnd gnd tx1 tx2 tvss rx aux vmid tvdd 57 8 29 27 30 6 v v power on detect oscin avdd avss oscout irq mfin mfout dvss 25 31 1 26 28 32 2 3 4 12 reset control power down control
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 5 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 8. pinning information 8.1 pin description fig 2. clrc632 pin con?guration clrc632 oscin oscout irq rstpd mfin vmid mfout rx tx1 avss tvdd aux tx2 avdd tvss dvdd ncs a2/sck nwr/r/nw/nwrite a1 nrd/nds/ndstrb a0/nwait/mosi dvss ale/as/nastrb/nss ad0/d0 d7/ad7 ad1/d1 d6/ad6 ad2/d2 d5/ad5 ad3/d3 d4/ad4 001aaj630 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 20 19 22 21 24 23 26 25 32 31 30 29 28 27 table 3. pin description pin symbol type [1] description 1 oscin i oscillator/clock inputs: crystal oscillator input to the oscillators inverting ampli?er externally generated clock input; f osc = 13.56 mhz 2 irq o interrupt request generates an output signaling an interrupt event 3 mfin i iso/iec 14443 a mifare serial data interface input 4 [2] mfout o interface outputs used as follows: mifare: generates serial data iso/iec 14443 a i-code: generates serial data based on i-code1 and iso/iec 15693 5 tx1 o transmitter 1 modulated carrier output; 13.56 mhz 6 tvdd p transmitter power supply for the tx1 and tx2 output stages 7 tx2 o transmitter 2 modulated carrier output; 13.56 mhz 8 tvss g transmitter ground for the tx1 and tx2 output stages 9 ncs i not chip select input is used to select and activate the clrc632s microprocessor interface 10 [3] nwr i not write input generates the strobe signal for writing data to the clrc632 registers when applied to pins d0 to d7 r/nw i read not write input is used to switch between read or write cycles nwrite i not write input selects the read or write cycle to be performed
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 6 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) [1] pin types: i = input, o = output, i/o = input/output, p = power and g = ground. [2] the slrc400 uses pin name sigout for pin mfout. the clrc632 functionality includes test functions for the slrc400 using pin mfout. [3] these pins provide different functionality depending on the selected microprocessor interface type (see section 9.1 on page 7 for detailed information). 11 [3] nrd i not read input generates the strobe signal for reading data from the clrc632 registers when applied to pins d0 to d7 nds i not data strobe input generates the strobe signal for the read and write cycles ndstrb i not data strobe input generates the strobe signal for the read and write cycles 12 dvss g digital ground 13 d0 o spi master in, slave out output 13 to 20 [3] d0 to d7 i/o 8-bit bidirectional data bus input/output on pins d0 to d7 ad0 to ad7 i/o 8-bit bidirectional address and data bus input/output on pins ad0 to ad7 21 [3] ale i address latch enable input for pins ad0 to ad5; high latches the internal address as i address strobe input for pins ad0 to ad5; high latches the internal address nastrb i not address strobe input for pins ad0 to ad5; low latches the internal address nss i not slave select strobe input for spi communication 22 [3] a0 i address line 0 is the address register bit 0 input nwait o not wait output: low starts an access cycle high ends an access cycle mosi i spi master out, slave in 23 a1 i address line 1 is the address register bit 1 input 24 [3] a2 i address line 2 is the address register bit 2 input sck i spi serial clock input 25 dvdd p digital power supply 26 avdd p analog power supply for pins oscin, oscout, rx, vmid and aux 27 aux o auxiliary output is used to generate analog test signals. the output signal is selected using the testanaselect registers testanaoutsel[4:0] bits 28 avss g analog ground 29 rx i receiver input is used as the card response input. the carrier is load modulated at 13.56 mhz, drawn from the antenna circuit 30 vmid p internal reference voltage pin provides the internal reference voltage as a supply remark: it must be connected to a 100 nf block capacitor connected between pin vmid and ground 31 rstpd i reset and power-down input: high: the internal current sinks are switched off, the oscillator is inhibited and the input pads are disconnected low (negative edge): start internal reset phase 32 oscout o crystal oscillator output for the oscillators inverting ampli?er table 3. pin description continued pin symbol type [1] description
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 7 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9. functional description 9.1 digital interface 9.1.1 overview of supported microprocessor interfaces the clrc632 supports direct interfacing to various 8-bit microprocessors. alternatively, the clrc632 can be connected to a pcs enhanced parallel port (epp). t ab le 4 shows the parallel interface signals supported by the clrc632. 9.1.2 automatic microprocessor interface detection after a power-on or hard reset, the clrc632 resets parallel microprocessor interface mode and detects the microprocessor interface type. the clrc632 identi?es the microprocessor interface using the logic levels on the control pins. this is performed using a combination of ?xed pin connections and the dedicated initialization routine (see section 9.7.4 on page 30 ). table 4. supported microprocessor and epp interface signals bus control signals bus separated address and data bus multiplexed address and data bus separated read and write strobes control nrd, nwr, ncs nrd, nwr, ncs, ale address a0, a1, a2 ad0, ad1, ad2, ad3, ad4, ad5 data d0 to d7 ad0 to ad7 common read and write strobe control r/nw, nds, ncs r/nw, nds, ncs, as address a0, a1, a2 ad0, ad1, ad2, ad3, ad4, ad5 data d0 to d7 ad0 to ad7 common read and write strobe with handshake (epp) control - nwrite, ndstrb, nastrb, nwait address - ad0, ad1, ad2, ad3, ad4, ad5 data - ad0 to ad7
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 8 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.1.3 connection to different microprocessor types the connection to various microprocessor types is shown in t ab le 5 . 9.1.3.1 separate read and write strobe refer to section 13.4.1 on page 102 for timing speci?cation. table 5. connection scheme for detecting the parallel interface type clrc632 pins parallel interface type and signals separated read/write strobe common read/write strobe dedicated address bus multiplexed address bus dedicated address bus multiplexed address bus multiplexed address bus with handshake ale high ale high as nastrb a2 a2 low a2 low high a1 a1 high a1 high high a0 a0 high a0 low nwait nrd nrd nrd nds nds ndstrb nwr nwr nwr r/nw r/nw nwrite ncs ncs ncs ncs ncs low d7 to d0 d7 to d0 ad7 to ad0 d7 to d0 ad7 to ad0 ad7 to ad0 fig 3. connection to microprocessor: separate read and write strobes 001aak607 address bus (a3 to an) ncs a0 to a2 address bus (a0 to a2) d0 to d7 ale data bus (d0 to d7) high nrd read strobe (nrd) nwr write strobe (nwr) clrc632 address decoder non-multiplexed address ncs ad0 to ad7 ale multiplexed address/data (ad0 to ad7) address latch enable (ale) nrd read strobe (nrd) nwr write strobe (nwr) a2 low a1 high a0 high clrc632 address decoder
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 9 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.1.3.2 common read and write strobe refer to section 13.4.2 on page 103 for timing speci?cation. 9.1.3.3 common read and write strobe: epp with handshake refer to section 13.4.3 on page 104 for timing speci?cation. remark: in the epp standard a chip select signal is not de?ned. to cover this situation, the status of the ncs pin can be used to inhibit the ndstrb signal. if this inhibitor is not used, it is mandatory that pin ncs is connected to pin dvss. remark: after each power-on or hard reset, the nwait signal on pin a0 is high-impedance. nwait is de?ned as the ?rst negative edge applied to the nastrb pin after the reset phase. the clrc632 does not support read address cycle. 9.1.4 serial peripheral interface the clrc632 provides compatibility with the 5-wire serial peripheral interface (spi) standard and acts as a slave during the spi communication. the spi clock signal sck must be generated by the master. data communication from the master to the slave uses the mosi line. the miso line sends data from the clrc632 to the master. fig 4. connection to microprocessor: common read and write strobes 001aak608 address bus (a3 to an) ncs a0 to a2 address bus (a0 to a2) d0 to d7 ale data bus (d0 to d7) high nrd data strobe (nds) nwr read/write (r/nw) clrc632 address decoder non-multiplexed address ncs ad0 to ad7 ale multiplexed address/data (ad0 to ad7) address strobe (as) nrd data strobe (nds) nwr read/write (r/nw) a2 low a1 high a0 low clrc632 address decoder fig 5. connection to microprocessor: epp common read/write strobes and handshake 001aak609 low ncs ad0 to ad7 ale multiplexed address/data (ad1 to ad8) address strobe (nastrb) nrd data strobe (ndstrb) nwr read/write (nwrite) a2 high a1 high a0 nwait clrc632
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 10 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) figure 6 shows the microprocessor connection to the clrc632 using spi. remark: the spi implementation for clrc632 conforms to the spi standard and ensures that the clrc632 can only be addressed as a slave. 9.1.4.1 spi read data the structure shown in t ab le 7 must be used to read data using spi. it is possible to read up to n-data bytes. the ?rst byte sent de?nes both, the mode and the address. the address byte must meet the following criteria: ? the most signi?cant bit (msb) of the ?rst byte sets the mode. to read data from the clrc632 the msb is set to logic 1 ? bits [6:1] de?ne the address ? the least signi?cant bit (lsb) should be set to logic 0. as shown in t ab le 8 , all the bits of the last byte sent are set to logic 0. table 6. spi compatibility clrc632 pins spi pins ale nss a2 sck a1 low a0 mosi nrd high nwr high ncs low d7 to d1 do not connect d0 miso fig 6. connection to microprocessor: spi 001aak610 low ncs d0 ale a2 sck a1 low mosi nss a0 miso clrc632 table 7. spi read data pin byte 0 byte 1 byte 2 ... byte n byte n + 1 mosi address 0 address 1 address 2 ... address n 00 miso xx data 0 data 1 ... data n - 1 data n
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 11 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) [1] all reserved bits must be set to logic 0. 9.1.4.2 spi write data the structure shown in t ab le 9 must be used to write data using spi. it is possible to write up to n-data bytes. the ?rst byte sent de?nes both the mode and the address. the address byte must meet the following criteria: ? the msb of the ?rst byte sets the mode. to write data to the clrc632, the msb is set to logic 0 ? bits [6:1] de?ne the address ? the lsb should be set to logic 0. spi write mode writes all data to the address de?ned in byte 0 enabling effective write cycles to the fifo buffer. [1] all reserved bits must be set to logic 0. remark: the data bus pins d7 to d0 must be disconnected. refer to section 13.4.4 on page 106 for the timing speci?cation. table 8. spi read address address (mosi) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) byte 0 1 address address address address address address reserved byte 1 to byte n reserved address address address address address address reserved byte n + 1 0 0000000 table 9. spi write data byte 0 byte 1 byte 2 ... byte n byte n + 1 mosi address data 0 data 1 ... data n - 1 data n miso xx xx xx ... xx xx table 10. spi write address address line (mosi) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) byte 0 0 address address address address address address reserved byte 1 to byte n+1 data data data data data data data data
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 12 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.2 memory organization of the eeprom table 11. eeprom memory organization diagram block byte address access memory content refer to position address 0 0 00h to 0fh r product information ?eld section 9.2.1 on page 13 1 1 10h to 1fh r/w startup register initialization ?le section 9.2.2.1 on page 14 2 2 20h to 2fh r/w 3 3 30h to 3fh r/w register initialization ?le user data or second initialization section 9.2.2.3 register initialization ? le (read/wr ite) on page 16 4 4 40h to 4fh r/w 5 5 50h to 5fh r/w 6 6 60h to 6fh r/w 7 7 70h to 7fh r/w 8 8 80h to 8fh w keys for crypto1 section 9.2.3 on page 18 9 9 90h to 9fh w 10 a a0h to afh w 11 b b0h to bfh w 12 c c0h to cfh w 13 d d0h to dfh w 14 e e0h to efh w 15 f f0h to ffh w 16 10 100h to 10fh w 17 11 110h to 11fh w 18 12 120h to 12fh w 19 13 130h to 13fh w 20 14 140h to 14fh w 21 15 150h to 15fh w 22 16 160h to 16fh w 23 17 170h to 17fh w 24 18 180h to 18fh w 25 19 190h to 19fh w 26 1a 1a0h to 1afh w 27 1b 1b0h to 1bfh w 28 1c 1c0h to 1cfh w 29 1d 1d0h to 1dfh w 30 1e 1e0h to 1efh w 31 1f 1f0h to 1ffh w
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 13 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.2.1 product information ?eld (read only) [1] byte 4 contains the current version number. 9.2.2 register initialization ?les (read/write) register initialization from address 10h to address 2fh is performed automatically during the initializing phase (see section 9.7.3 on page 30 ) using the startup register initialization ?le. in addition, the clrc632 registers can be initialized using values from the register initialization ?le when the loadcon?g command is executed (see section 11.5.1 on page 95 ). table 12. product information ?eld byte symbol access value description 15 crc r - the content of the product information ?eld is secured using a crc byte which is checked during start-up 14 rsmaxp r - maximum source resistance for the p-channel driver transistor on pins tx1 and tx2 the source resistance of the p-channel driver transistors of pin tx1 and tx2 can be adjusted using the value gscfgcw[5:0] in the cwconductance register (see section 9.9.3 on page 32 ). the mean value of the maximum adjustable source resistance for pins tx1 and tx2 is stored as an integer value in w in this byte. typical values for rsmaxp are between 60 w to 140 w . this value is denoted as maximum adjustable source resistance r s(ref)maxp and is measured by setting the cwconductance registers gscfgcw[5:0] bits to 01h. 13 to 12 internal r - two bytes for internal trimming parameters 11 to 8 product serial number r - a unique four byte serial number for the device 7 to 5 reserved r - 4 to 0 product type identi?cation r - the clrc632 is a member of a new family of highly integrated reader ics. each member of the product family has a unique product type identi?cation. the value of the product type identi?cation is shown in t ab le 13 . table 13. product type identi?cation de?nition de?nition product type identi?cation bytes byte 0 1 2 3 4 [1] value 30h ffh ffh 0fh xxh
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 14 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) remark: the following points apply to initialization: ? the page register (addressed using 10h, 18h, 20h, 28h) is skipped and not initialized. ? make sure that all presetxx registers are not changed. ? make sure that all register bits that are reserved are set to logic 0. 9.2.2.1 startup register initialization ?le (read/write) the eeprom memory block address 1 and 2 contents are used to automatically set the register subaddresses 10h to 2fh during the initialization phase. the default values stored in the eeprom during production are shown in section 9.2.2.2 f actor y def ault star tup register initialization ? le . the byte assignment is shown in t ab le 14 . 9.2.2.2 factory default startup register initialization ?le during the production tests, the startup register initialization ?le is initialized using the default values shown in t ab le 15 . during each power-up and initialization phase, these values are written to the clrc632s registers. table 14. byte assignment for register initialization at start-up eeprom byte address register address remark 10h (block 1, byte 0) 10h skipped 11h 11h copied 2fh (block 2, byte 15) 2fh copied
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 15 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) remark: the clrc632 default con?guration supports the mifare and iso/iec 14443 a communication scheme. memory addresses 3 to 7 may be used for user-speci?c initialization ?les such as i-code1, iso/iec 15693 or iso/iec 14443 b. table 15. shipment content of startup con?guration ?le eeprom byte address register address value symbol description 10h 10h 00h page free for user 11h 11h 58h txcontrol transmitter pins tx1 and tx2 are switched off, bridge driver con?guration, modulator driven from internal digital circuitry 12h 12h 3fh cwconductance source resistance of tx1 and tx2 is set to minimum 13h 13h 3fh modconductance de?nes the output conductance 14h 14h 19h codercontrol iso/iec 14443 a coding is set 15h 15h 13h modwidth pulse width for miller pulse coding is set to standard con?guration 16h 16h 3fh modwidthsof pulse width of start of frame (sof) 17h 17h 3bh typeframing iso/iec 14443 a framing is set 18h 18h 00h page free for user 19h 19h 73h rxcontrol1 iso/iec 14443 a is set and internal ampli?er gain is maximum 1ah 1ah 08h decodercontrol bit-collisions always evaluate to high in the data bit stream 1bh 1bh adh bitphase bitphase[7:0] is set to standard con?guration 1ch 1ch ffh rxthreshold minlevel[3:0] and colllevel[3:0] are set to maximum 1dh 1dh 1eh bpskdemcontrol iso/iec 14443 a is set 1eh 1eh 41h rxcontrol2 use q-clock for the receiver, automatic receiver off is switched on, decoder is driven from internal analog circuitry 1fh 1fh 00h clockqcontrol automatic q-clock calibration is switched on 20h 20h 00h page free for user 21h 21h 06h rxwait frame guard time is set to six bit-clocks 22h 22h 03h channelredundancy channel redundancy is set using iso/iec 14443 a 23h 23h 63h crcpresetlsb crc preset value is set using iso/iec 14443 a 24h 24h 63h crcpresetmsb crc preset value is set using iso/iec 14443 a 25h 25h 00h timeslotperiod de?nes the time for the i-code1 time slots 26h 26h 00h mfoutselect pin mfout is set low 27h 27h 00h preset27 - 28h 28h 00h page free for user 29h 29h 08h fifolevel waterlevel[5:0] fifo buffer warning level is set to standard con?guration 2ah 2ah 07h timerclock tprescaler[4:0] is set to standard con?guration, timer unit restart function is switched off 2bh 2bh 06h timercontrol timer is started at the end of transmission, stopped at the beginning of reception 2ch 2ch 0ah timerreload treloadvalue[7:0]: the timer unit preset value is set to standard con?guration 2dh 2dh 02h irqpincon?g pin irq is set to high-impedance 2eh 2eh 00h preset2e - 2fh 2fh 00h preset2f -
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 16 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.2.2.3 register initialization ?le (read/write) the eeprom memory content from block address 3 to 7 can initialize register sub addresses 10h to 2fh when the loadcon?g command is executed (see section 11.5.1 on page 95 ). this command requires the eeprom starting byte address as a two byte argument for the initialization procedure. the byte assignment is shown in t ab le 16 . the register initialization ?le is large enough to hold values for two initialization sets and up to one block (16-byte) of user data. the startup con?guration could be adapted to the i-code1 startup con?guration and stored in register block address 3 and 4, providing additional ?exibility. remark: the register initialization ?le can be read/written by users and these bytes can be used to store other user data. after each power-up, the default con?guration enables the mifare and iso/iec 14443 a protocol. 9.2.2.4 content of i-code1 and iso/iec 15693 startup register values t ab le 17 gives an overview of the startup values for i-code1 and iso/iec 15693 communication. table 16. byte assignment for register initialization at startup eeprom byte address register address remark eeprom starting byte address 10h skipped eeprom + 1 starting byte address 11h copied eeprom + 31 starting byte address 2fh copied
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 17 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) table 17. content of i-code1 startup con?guration eeprom byte address register address value symbol description 30h 10h 00h page free for user 31h 11h 58h txcontrol transmitter pins tx1 and tx2 switched off, bridge driver con?guration, modulator driven from internal digital circuitry 32h 12h 3fh cwconductance source resistance (r s ) of tx1 and tx2 to minimum 33h 13h 05h modgscfgh source resistance (r s ) of tx1 and tx2 at the time of modulation, to determine the modulation index 34h 14h 2ch codercontrol selects the bit coding mode and the framing during transmission 35h 15h 3fh modwidth pulse width for code used (1 out of 256, nrz or 1 out of 4) pulse coding is set to standard con?guration 36h 16h 3fh modwidthsof pulse width of sof 37h 17h 00h typebframing - 38h 18h 00h page free for user 39h 19h 8bh rxcontrol1 ampli?er gain is maximum 3ah 1ah 00h decodercontrol bit-collisions always evaluate to high in the data bit stream 3bh 1bh 54h bitphase bitphase[7:0] is set to standard con?guration 3ch 1ch 68h rxthreshold: minlevel[3:0] and colllevel[3:0] are set to maximum 3dh 1dh 00h bpskdemcontrol - 3eh 1eh 41h rxcontrol2 use q-clock for the receiver, automatic receiver off is switched on, decoder is driven from internal analog circuitry 3fh 1fh 00h clockqcontrol automatic q-clock calibration is switched on 40h 20h 00h page free for user 41h 21h 08h rxwait frame guard time is set to eight bit-clocks 42h 22h 0ch channelredundancy channel redundancy is set using i-code1 43h 23h feh crcpresetlsb crc preset value is set using i-code1 44h 24h ffh crcpresetmsb crc preset value is set using i-code1 45h 25h 00h timeslot period de?nes the time for the i-code1 time slots 46h 26h 00h mfoutselect pin mfout is set low 47h 27h 00h preset27 - 48h 28h 00h page free for user 49h 29h 3eh fifolevel waterlevel[5:0] fifo buffer warning level is set to standard con?guration 4ah 2ah 0bh timerclock tprescaler[4:0] is set to standard con?guration, timer unit restart function is switched off 4bh 2bh 02h timercontrol timer is started at the end of transmission, stopped at the beginning of reception 4ch 2ch 00h timerreload the timer unit preset value is set to standard con?guration 4dh 2dh 02h irqpincon?g pin irq is set to high-impedance 4eh 2eh 00h preset2e - 4fh 2fh 00h preset2f -
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 18 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.2.3 crypto1 keys (write only) mifare security requires speci?c cryptographic keys to encrypt data stream communication on the contactless interface. these keys are called crypto1 keys. 9.2.3.1 key format keys stored in the eeprom are written in a speci?c format. each key byte must be split into lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble). each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. this format is a precondition for successful execution of the loadkeye2 (see section 11.7.1 on page 97 ) and loadkey commands (see section 11.7.2 on page 97 ). using this format, 12 bytes of eeprom memory are needed to store a 6-byte key. this is shown in figure 7 . example : the value for the key must be written to the eeprom. ? if the key was: a0h a1h a2h a3h a4h a5h then ? 5ah f0h 5ah e1h 5ah d2h 5ah c3h 5ah b4h 5ah a5h would be written. remark: it is possible to load data for other key formats into the eeprom key storage location. however, it is not possible to validate card authentication with data which will cause the loadkeye2 command (see section 11.7.1 on page 97 ) to fail. 9.2.3.2 storage of keys in the eeprom the clrc632 reserves 384 bytes of memory in the eeprom for the crypto1 keys. no memory segmentation is used to mirror the 12-byte structure of key storage. thus, every byte of the dedicated memory area can be the start of a key. example : if the key loading cycle starts at the last byte address of an eeprom block, (for example, key byte 0 is stored at 12fh), the next bytes are stored in the next eeprom block, for example, key byte 1 is stored at 130h, byte 2 at 131h up to byte 11 at 13ah. based on the 384 bytes of memory and a single key needing 12 bytes, then up to 32 different keys can be stored in the eeprom. remark: it is not possible to load a key exceeding the eeprom byte location 1ffh. fig 7. key storage format 001aak640 0 (lsb) master key byte master key bits eeprom byte address example k7 k6 k5 k4 k7 k6 k5 k4 n 5ah k3 k2 k1 k0 k3 k2 k1 k0 n + 1 f0h 1 k7 k6 k5 k4 k7 k6 k5 k4 n + 2 5ah k3 k2 k1 k0 k3 k2 k1 k0 n + 3 e1h 5 (msb) k7 k6 k5 k4 k7 k6 k5 k4 n + 10 5ah k3 k2 k1 k0 k3 k2 k1 k0 n + 11 a5h
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 19 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.3 fifo buffer an 8 64 bit fifo buffer is used in the clrc632 to act as a parallel-to-parallel converter. it buffers both the input and output data streams between the microprocessor and the internal circuitry of the clrc632. this makes it possible to manage data streams up to 64 bytes long without needing to take timing constraints into account. 9.3.1 accessing the fifo buffer 9.3.1.1 access rules the fifo buffer input and output data bus is connected to the fifodata register. writing to this register stores one byte in the fifo buffer and increments the fifo buffer write pointer. reading from this register shows the fifo buffer contents stored at the fifo buffer read pointer and increments the fifo buffer read pointer. the distance between the write and read pointer can be obtained by reading the fifolength register. when the microprocessor starts a command, the clrc632 can still access the fifo buffer while the command is running. only one fifo buffer has been implemented which is used for input and output. therefore, the microprocessor must ensure that there are no inadvertent fifo buffer accesses. t ab le 18 gives an overview of fifo buffer access during command processing. 9.3.2 controlling the fifo buffer in addition to writing to and reading from the fifo buffer, the fifo buffer pointers can be reset using the flushfifo bit. this changes the fifolength[6:0] value to zero, bit fifoov? is cleared and the stored bytes are no longer accessible. this enables the fifo buffer to be written with another 64 bytes of data. table 18. fifo buffer access active command fifo buffer remark m p write m p read startup - - idle - - transmit yes - receive - yes transceive yes yes the microprocessor has to know the state of the command (transmitting or receiving) writee2 yes - reade2 yes yes the microprocessor has to prepare the arguments, afterwards only reading is allowed loadkeye2 yes - loadkey yes - authent1 yes - authent2 - - loadcon?g yes - calccrc yes -
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 20 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.3.3 fifo buffer status information the microprocessor can get the following fifo buffer status data: ? the number of bytes stored in the fifo buffer: bits fifolength[6:0] ? the fifo buffer full warning: bit hialert ? the fifo buffer empty warning: bit loalert ? the fifo buffer over?ow warning: bit fifoov?. remark: setting the flushfifo bit clears the fifoov? bit. the clrc632 can generate an interrupt signal when: ? bit loalertirq is set to logic 1 and bit loalert = logic 1, pin irq is activated. ? bit hialertirq is set to logic 1 and bit hialert = logic 1, pin irq activated. the hialert ?ag bit is set to logic 1 only when the waterlevel[5:0] bits or less can be stored in the fifo buffer. the trigger is generated by equation 1 : (1) the loalert ?ag bit is set to logic 1 when the fifolevel registers waterlevel[5:0] bits or less are stored in the fifo buffer. the trigger is generated by equation 2 : (2) 9.3.4 fifo buffer registers and ?ags t ab le 18 shows the related fifo buffer ?ags in alphabetic order. 9.4 interrupt request system the clrc632 indicates interrupt events by setting the primarystatus register bit irq (see section 10.5.1.4 pr imar ystatus register on page 51 ) and activating pin irq. the signal on pin irq can be used to interrupt the microprocessor using its interrupt handling capabilities ensuring ef?cient microprocessor software. hialert 64 fifolength C () waterlevel = loalert fifolength waterlevel = table 19. associated fifo buffer registers and ?ags flags register name bit register address fifolength[6:0] fifolength 6 to 0 04h fifoov? errorflag 4 0ah flushfifo control 0 09h hialert primarystatus 1 03h hialertien interrupten 1 06h hialertirq interruptrq 1 07h loalert primarystatus 0 03h loalertien interrupten 0 06h loalertirq interruptrq 0 07h waterlevel[5:0] fifolevel 5 to 0 29h
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 21 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.4.1 interrupt sources overview t ab le 20 shows the integrated interrupt ?ags, related source and setting condition. the interrupt timerirq ?ag bit indicates an interrupt set by the timer unit. bit timerirq is set when the timer decrements from one down to zero (bit tautorestart disabled) or from one to the treloadvalue[7:0] with bit tautorestart enabled. bit txirq indicates interrupts from different sources and is set as follows: ? the transmitter automatically sets the bit txirq interrupt when it is active and its state changes from sending data to transmitting the end of frame pattern ? the crc coprocessor sets the bit txirq after all data from the fifo buffer has been processed indicated by bit crcready = logic 1 ? when eeprom programming is ?nished, the bit txirq is set and is indicated by bit e2ready = logic 1 the rxirq ?ag bit indicates an interrupt when the end of the received data is detected. the idleirq ?ag bit is set when a command ?nishes and the content of the command register changes to idle. when the fifo buffer reaches the high-level indicated by the waterlevel[5:0] value (see section 9.3.3 on page 20 ) and bit hialert = logic 1, then the hialertirq ?ag bit is set to logic 1. when the fifo buffer reaches the low-level indicated by the waterlevel[5:0] value (see section 9.3.3 on page 20 ) and bit loalert = logic 1, then loalertirq ?ag bit is set to logic 1. 9.4.2 interrupt request handling 9.4.2.1 controlling interrupts and getting their status the clrc632 informs the microprocessor about the interrupt request source by setting the relevant bit in the interruptrq register. the relevance of each interrupt request bit as source for an interrupt can be masked by the interrupten register interrupt enable bits. table 20. interrupt sources interrupt ?ag interrupt source trigger action timerirq timer unit timer counts from 1 to 0 txirq transmitter a data stream, transmitted to the card, ends crc coprocessor all data from the fifo buffer has been processed eeprom all data from the fifo buffer has been programmed rxirq receiver a data stream, received from the card, ends idleirq command register command execution ?nishes hialertirq fifo buffer fifo buffer is full loalertirq fifo buffer fifo buffer is empty table 21. interrupt control registers register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 interrupten setien reserved timerien txien rxien idleien hialertien loalertien interruptrq setirq reserved timerirq txirq rxirq idleirq hialertirq loalertirq
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 22 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) if any interrupt request ?ag is set to logic 1 (showing that an interrupt request is pending) and the corresponding interrupt enable ?ag is set, the primarystatus register irq ?ag bit is set to logic 1. different interrupt sources can activate simultaneously because all interrupt request bits are ored, coupled to the irq ?ag and then forwarded to pin irq. 9.4.2.2 accessing the interrupt registers the interrupt request bits are automatically set by the clrc632s internal state machines. in addition, the microprocessor can also set or clear the interrupt request bits as required. a special implementation of the interruptrq and interrupten registers enables changing an individual bit status without in?uencing any other bits. if an interrupt register is set to logic 1, bit setixx and the speci?c bit must both be set to logic 1 at the same time. vice versa, if a speci?c interrupt ?ag is cleared, zero must be written to the setixx and the interrupt register address must be set to logic 1 at the same time. if a content bit is not changed during the setting or clearing phase, zero must be written to the speci?c bit location. example: writing 3fh to the interruptrq register clears all bits. setirq is set to logic 0 while all other bits are set to logic 1. writing 81h to the interruptrq register sets loalertirq to logic 1 and leaves all other bits unchanged. 9.4.3 con?guration of pin irq the logic level of the irq ?ag bit is visible on pin irq. the signal on pin irq can also be controlled using the following irqpincon?g register bits. ? bit irqinv: the signal on pin irq is equal to the logic level of bit irq when this bit is set to logic 0. when set to logic 1, the signal on pin irq is inverted with respect to bit irq. ? bit irqpushpull: when set to logic 1, pin irq has cmos output characteristics. when it is set to logic 0, it is an open-drain output which requires an external resistor to achieve a high-level at pin irq. remark: during the reset phase (see section 9.7.2 on page 29 ) bit irqinv is set to logic 1 and bit irqpushpull is set to logic 0. this results in a high-impedance on pin irq.
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 23 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.4.4 register overview interrupt request system t ab le 22 shows the related interrupt request system ?ags in alphabetic order. 9.5 timer unit the timer derives its clock from the 13.56 mhz on-board chip clock. the microprocessor can use this timer to manage timing-relevant tasks. the timer unit may be used in one of the following con?gurations: ? timeout counter ? watchdog counter ? stopwatch ? programmable one shot ? periodical trigger the timer unit can be used to measure the time interval between two events or to indicate that a speci?c timed event occurred. the timer is triggered by events but does not in?uence any event (e.g. a time-out during data receiving does not automatically in?uence the receiving process). several timer related ?ags can be set and these ?ags can be used to generate an interrupt. table 22. associated interrupt request system registers and ?ags flags register name bit register address hialertien interrupten 1 06h hialertirq interruptrq 1 07h idleien interrupten 2 06h idleirq interruptrq 2 07h irq primarystatus 3 03h irqinv irqpincon?g 1 07h irqpushpull irqpincon?g 0 07h loalertien interrupten 0 06h loalertirq interruptrq 0 07h rxien interrupten 3 06h rxirq interruptrq 3 07h setien interrupten 7 06h setirq interruptrq 7 07h timerien interrupten 5 06h timerirq interruptrq 5 07h txien interrupten 4 06h txirq interruptrq 4 07h
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 24 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.5.1 timer unit implementation 9.5.1.1 timer unit block diagram figure 8 shows the block diagram of the timer module. the timer unit is designed, so that events when combined with enabling ?ags start or stop the counter. for example, setting bit tstarttxbegin = logic 1 enables control of received data with the timer unit. in addition, the ?rst received bit is indicated by the txbegin event. this combination starts the counter at the de?ned treloadvalue[7:0]. the timer stops automatically when the counter value is equal to zero or if a de?ned stop event happens. 9.5.1.2 controlling the timer unit the main part of the timer unit is a down-counter. as long as the down-counter value is not zero, it decrements its value with each timer clock cycle. if the tautorestart ?ag is enabled, the timer does not decrement down to zero. on reaching value 1, the timer reloads the next clock function with the treloadvalue[7:0]. fig 8. timer module block diagram 001aak611 txend event tautorestart trunning tstarttxend tstartnow s r q start counter/ parallel load stop counter tprescaler[4:0] timervalue[7:0] counter = 0 ? to interrupt logic: timerirq parallel out parallel in treloadvalue[7:0] clock divider counter module (x x - 1) tstopnow txbegin event tstarttxbegin tstoprxend rxend event tstoprxbegin 13.56 mhz to parallel interface rxbegin event q
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 25 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) the timer is started immediately by loading a value from the timerreload register into the counter module. this is activated by one of the following events: ? transmission of the ?rst bit to the card (txbegin event) with bit tstarttxbegin = logic 1 ? transmission of the last bit to the card (txend event) with bit tstarttxend = logic 1 ? bit tstartnow is set to logic 1 by the microprocessor remark: every start event reloads the timer from the timerreload register. thus, the timer unit is re-triggered. the timer can be con?gured to stop on one of the following events: ? receipt of the ?rst valid bit from the card (rxbegin event) with bit tstoprxbegin = logic 1 ? receipt of the last bit from the card (rxend event) with bit tstoprxend = logic 1 ? the counter module has decremented down to zero and bit tautorestart = logic 0 ? bit tstopnow is set to logic 1 by the microprocessor. loading a new value, e.g. zero, into the timerreload register or changing the timer unit while it is counting will not immediately in?uence the counter. in both cases, this is because this register only affects the counter content after a start event. if the counter is stopped when bit tstopnow is set, no timerirq is ?agged. 9.5.1.3 timer unit clock and period the timer unit clock is derived from the 13.56 mhz on-board chip clock using the programmable divider. clock selection is made using the timerclock register tprescaler[4:0] bits based on equation 3 : (3) the values for the tprescaler[4:0] bits are between 0 and 21 which results in a minimum periodic time (t timerclock ) of between 74 ns and 150 ms. the time period elapsed since the last start event is calculated using equation 4 : (4) this results in a minimum time period (t timer ) of between 74 ns and 40 s. 9.5.1.4 timer unit status the secondarystatus registers trunning bit shows the timers status. con?gured start events start the timer at the treloadvalue[7:0] and changes the status ?ag trunning to logic 1. conversely, con?gured stop events stop the timer and sets the trunning status ?ag to logic 0. as long as status ?ag trunning is set to logic 1, the timervalue register changes on the next timer unit clock cycle. the timervalue[7:0] bits can be read directly from the timervalue register. f timerclock 1 t timerclock --------------------------- - 2 tprescaler 13.56 -------------------------- mhz ] [ == t timer treloadvalue timervalue C f timerclock ---------------------------------------------------------------------------- - s [] =
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 26 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.5.1.5 timeslotperiod when sending i-code1 quit frames, it is necessary to generate the exact chronological relationship to the start of the command frame. if at the end of command execution timeslotperiod > 0, the timeslotperiod starts. if the fifo buffer contains data when the end of timeslotperiod is reached, the data is sent. if the fifo buffer is empty nothing happens. as long as the timeslotperiod is > 0, the timeslotperiod counter automatically starts on reaching the end. this forms the exact time relationship between the start and ?nish of the command frame used to generate and send i-code1 quit frames. when the timeslotperiod > 0, the next frame starts with exactly the same interval timeslotperiod/coderrate delayed after each previous send frame. coderrate de?nes the clock frequency of the encoder. if timeslotperiod[7:0] = 0, the send function is not automatically triggered. the content of the timeslotperiod register can be changed while it is running but the change is only effective after the next timeslotperiod restart. example : ? coderrate = 0 0.5 (~52.97 khz) ? the interval should be 8.458 ms for i-code1 standard mode ? remark: the timeslotperiodmsb bit is contained in the mfoutselect register. remark: set bit txcrcen to logic 0 before the quit frame is sent. if txcrcen is not set to logic 0, the quit frame is sent with a calculated crc value. use the crc8 algorithm to calculate the quit value. fig 9. timeslotperiod table 23. timeslotperiod i-code1 mode timeslotperiod for tsp1 timeslotperiod for tsp2 standard mode bfh 1bfh fast mode 5fh 67h timeslotperiod coderrate interval = 52.97 khz 8.458 ms 1 447 1bfh == C = 001aak612 command response1 response2 tsp2 tsp1 quit1 quit2
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 27 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.5.2 using the timer unit functions 9.5.2.1 time-out and watchdog counters after starting the timer using treloadvalue[7:0], the timer unit decrements the timervalue register beginning with a given start event. if a given stop event occurs, such as a bit being received from the card, the timer unit stops without generating an interrupt. if a stop event does not occur, such as the card not answering within the expected time, the timer unit decrements down to zero and generates a timer interrupt request. this signals to the microprocessor the expected event has not occurred within the given time (t timer ). 9.5.2.2 stopwatch the time (t timer ) between a start and stop event is measured by the microprocessor using the timer unit. setting the treloadvalue register triggers the timer which in turn, starts to decrement. if the de?ned stop event occurs, the timer stops. the time between start and stop is calculated by the microprocessor using equation 5 , when the timer does not decrement down to zero. (5) 9.5.2.3 programmable one shot timer and periodic trigger programmable one shot timer: the microprocessor starts the timer unit and waits for the timer interrupt. the interrupt occurs after the time speci?ed by t timer . periodic trigger: if the microprocessor sets the tautorestart bit, it generates an interrupt request after every t timer cycle. 9.5.3 timer unit registers t ab le 24 shows the related ?ags of the timer unit in alphabetical order. d t treload value timervalue C () t timer = table 24. associated timer unit registers and ?ags flags register name bit register address tautorestart timerclock 5 2ah timervalue[7:0] timervalue 7 to 0 0ch treloadvalue[7:0] timerreload 7 to 0 2ch tprescaler[4:0] timerclock 4 to 0 2ah trunning secondarystatus 7 05h tstartnow control 1 09h tstarttxbegin timercontrol 0 2bh tstarttxend timercontrol 1 2bh tstopnow control 2 09h tstoprxbegin timercontrol 2 2bh tstoprxend timercontrol 3 2bh
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 28 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.6 power reduction modes 9.6.1 hard power-down hard power-down is enabled when pin rstpd is high. this turns off all internal current sinks including the oscillator. all digital input buffers are separated from the input pads and de?ned internally (except pin rstpd itself). the output pins are frozen at a given value. the status of all pins during a hard power-down is shown in t ab le 25 . 9.6.2 soft power-down mode soft power-down mode is entered immediately using the control register bit powerdown. all internal current sinks, including the oscillator buffer, are switched off. the digital input buffers are not separated from the input pads and keep their functionality. in addition, the digital output pins do not change their state. after resetting the control register bit powerdown, the bit indicating soft power-down mode is only cleared after 512 clock cycles. resetting it does not immediately clear it. the powerdown bit is automatically cleared when the soft power-down mode is exited. remark: when the internal oscillator is used, time (t osc ) is required for the oscillator to become stable. this is because the internal oscillator is supplied by v dda and any clock cycles will not be detected by the internal logic until v dda is stable. table 25. signal on pins during hard power-down symbol pin type description oscin 1 i not separated from input, pulled to avss irq 2 o high-impedance mfin 3 i separated from input mfout 4 o low tx1 5 o high, if bit tx1rfen = logic 1 low, if bit tx1rfen = logic 0 tx2 7 o high, only if bit tx2rfen = logic 1 and bit tx2inv = logic 0 otherwise low ncs 9 i separated from input nwr 10 i separated from input nrd 11 i separated from input d0 to d7 13 to 20 i/o separated from input ale 21 i separated from input a0 22 i/o separated from input a1 23 i separated from input a2 24 i separated from input aux 27 o high-impedance rx 29 i not changed vmid 30 a pulled to v dda rstpd 31 i not changed oscout 32 o high
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 29 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.6.3 standby mode the standby mode is immediately entered when the control register standby bit is set. all internal current sinks, including the internal digital clock buffer are switched off. however, the oscillator buffer is not switched off. the digital input buffers are not separated by the input pads, keeping their functionality and the digital output pins do not change their state. in addition, the oscillator does not need time to wake-up. after resetting the control register standby bit, it takes four clock cycles on pin oscin for standby mode to exit. resetting bit standby does not immediately clear it. it is automatically cleared when the standby mode is exited. 9.6.4 automatic receiver power-down it is a power saving feature to switch off the receiver circuit when it is not needed. setting bit rxautopd = logic 1, automatically powers down the receiver when it is not in use. setting bit rxautopd = logic 0, keeps the receiver continuously powered up. 9.7 startup phase the events executed during the startup phase are shown in figure 10 . 9.7.1 hard power-down phase the hard power-down phase is active during the following cases: ? a power-on reset (por) caused by power-up on pins dvdd or avdd activated when v ddd or v dda is below the digital reset threshold. ? a high-level on pin rstpd which is active while pin rstpd is high. the high level period on pin rstpd must be at least 100 m s (t pd 3 100 m s). shorter phases will not necessarily result in the reset phase (t reset ). the rising or falling edge slew rate on pin rstpd is not critical because pin rstpd is a schmitt trigger input. 9.7.2 reset phase the reset phase automatically follows the hard power-down. once the oscillator is running stably, the reset phase takes 512 clock cycles. during the reset phase, some register bits are preset by hardware. the respective reset values are given in the description of each register (see section 10.5 on page 50 ). remark: when the internal oscillator is used, time (t osc ) is required for the oscillator to become stable. this is because the internal oscillator is supplied by v dda and any clock cycles will not be detected by the internal logic until v dda is stable. fig 10. the startup procedure 001aak613 startup phase states t rstpd t reset t init hard power- down phase reset phase initialising phase ready
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 30 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.7.3 initialization phase the initialization phase automatically follows the reset phase and takes 128 clock cycles. during the initializing phase the content of the eeprom blocks 1 and 2 is copied into the register subaddresses 10h to 2fh (see section 9.2.2 on page 13 ). remark: during the production test, the clrc632 is initialized with default con?guration values. this reduces the microprocessors con?guration time to a minimum. 9.7.4 initializing the parallel interface type a different initialization sequence is used for each microprocessor. this enables detection of the correct microprocessor interface type and synchronization of the microprocessors and the clrc632s start-up. see section 9.1.3 on page 8 for detailed information on the different connections for each microprocessor interface type. during startup phase, the command value is set to 3fh once the oscillator attains clock frequency stability at an amplitude of > 90 % of the nominal 13.56 mhz clock frequency. at the end of the initialization phase, the clrc632 automatically switches to idle and the command value changes to 00h. to ensure correct detection of the microprocessor interface, the following sequence is executed: ? the command register is read until the 6-bit register value is 00h. on reading the 00h value, the internal initialization phase is complete and the clrc632 is ready to be controlled ? write 80h to the page register to initialize the microprocessor interface ? read the command register. if it returns a value of 00h, the microprocessor interface was successfully initialized ? write 00h to the page registers to activate linear addressing mode. 9.8 oscillator circuit the clock applied to the clrc632 acts as a time basis for the synchronous system encoder and decoder. the stability of the clock frequency is an important factor for correct operation. to obtain highest performance, clock jitter must be as small as possible. this is best achieved by using the internal oscillator buffer with the recommended circuitry. fig 11. quartz clock connection 001aak614 13.56 mhz 15 pf 15 pf oscout oscin clrc632
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 31 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) if an external clock source is used, the clock signal must be applied to pin oscin. in this case, be very careful in optimizing clock duty cycle and clock jitter. ensure the clock quality has been veri?ed. it must meet the speci?cations described in section 13.4.5 on page 106 . remark: we do not recommend using an external clock source. 9.9 transmitter pins tx1 and tx2 the signal on pins tx1 and tx2 is the 13.56 mhz energy carrier modulated by an envelope signal. it can be used to drive an antenna directly, using minimal passive components for matching and ?ltering (see section 15.1 on page 107 ). to enable this, the output circuitry is designed with a very low-impedance source resistance. the txcontrol register is used to control the tx1 and tx2 signals. 9.9.1 con?guring pins tx1 and tx2 tx1 pin con?gurations are described in t ab le 26 . tx2 pin con?gurations are described in t ab le 27 . table 26. pin tx1 con?gurations txcontrol register con?guration envelope tx1 signal tx1rfen force100ask 0 x x low (gnd) 1 0 0 13.56 mhz carrier frequency modulated 1 0 1 13.56 mhz carrier frequency 110low 1 1 1 13.56 mhz energy carrier
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 32 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.9.2 antenna operating distance versus power consumption using different antenna matching circuits (by varying the supply voltage on the antenna driver supply pin tvdd), it is possible to ?nd the trade-off between maximum effective operating distance and power consumption. different antenna matching circuits are described in the application note mifare design of mfrc500 matching circuit and antennas . 9.9.3 antenna driver output source resistance the output source conductance of pins tx1 and tx2 can be adjusted between 1 w and 100 w using the cwconductance register gscfgcw[5:0] bits. the output source conductance of pins tx1 and tx2 during the modulation phase can be adjusted between 1 w and 100 w using the modconductance register gscfgmod[5:0] bits. the values are relative to the reference resistance (r s(ref) ) which is measured during the production test and stored in the clrc632 eeprom. it can be read from the product information ?eld (see section 9.2.1 on page 13 ). the electrical speci?cation can be found in section 13.3.3 on page 101 . table 27. pin tx2 con?gurations txcontrol register con?guration envelope tx2 signal tx2rfen force100ask tx2cw tx2inv 0x xxxlow 1 0 0 0 0 13.56 mhz carrier frequency modulated 1 0 0 0 1 13.56 mhz carrier frequency 1 0 0 1 0 13.56 mhz carrier frequency modulated, 180 phase-shift relative to tx1 1 0 0 1 1 13.56 mhz carrier frequency, 180 phase-shift relative to tx1 1 0 1 0 x 13.56 mhz carrier frequency 1 0 1 1 x 13.56 mhz carrier frequency, 180 phase-shift relative to tx1 11 000low 1 1 0 0 1 13.56 mhz carrier frequency 1 1 0 1 0 high 1 1 0 1 1 13.56 mhz carrier frequency, 180 phase-shift relative to tx1 1 1 1 0 x 13.56 mhz carrier frequency 1 1 1 1 x 13.56 mhz carrier frequency, 180 phase-shift relative to tx1
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 33 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.9.3.1 source resistance table table 28. tx1 and tx2 source resistance of n-channel driver transistor against gscfgcw or gscfgmod mant = mantissa; exp= exponent. gscfgcw, gscfgmod (decimal) exp gscfgcw , exp gscfgmod (decimal) mant gscfgcw , mant gscfgmod (decimal) r s(ref) ( w ) gscfgcw, gscfgmod (decimal) exp gscfgcw , exp gscfgmod (decimal) mant gscfgcw , mant gscfgmod (decimal) r s(ref) ( w ) 0 0 0 - 24 1 8 0.0652 16 1 0 - 25 1 9 0.0580 32 2 0 - 37 2 5 0.0541 48 3 0 - 26 1 10 0.0522 1 0 1 1.0000 27 1 11 0.0474 17 1 1 0.5217 51 3 3 0.0467 2 0 2 0.5000 38 2 6 0.0450 3 0 3 0.3333 28 1 12 0.0435 33 2 1 0.2703 29 1 13 0.0401 18 1 2 0.2609 39 2 7 0.0386 4 0 4 0.2500 30 1 14 0.0373 5 0 5 0.2000 52 3 4 0.0350 19 1 3 0.1739 31 1 15 0.0348 6 0 6 0.1667 40 2 8 0.0338 7 0 7 0.1429 41 2 9 0.0300 49 3 1 0.1402 53 3 5 0.0280 34 2 2 0.1351 42 2 10 0.0270 20 1 4 0.1304 43 2 11 0.0246 8 0 8 0.1250 54 3 6 0.0234 9 0 9 0.1111 44 2 12 0.0225 21 1 5 0.1043 45 2 13 0.0208 10 0 10 0.1000 55 3 7 0.0200 11 0 11 0.0909 46 2 14 0.0193 35 2 3 0.0901 47 2 15 0.0180 22 1 6 0.0870 56 3 8 0.0175 12 0 12 0.0833 57 3 9 0.0156 13 0 13 0.0769 58 3 10 0.0140 23 1 7 0.0745 59 3 11 0.0127 14 0 14 0.0714 60 3 12 0.0117 50 3 2 0.0701 61 3 13 0.0108 36 2 4 0.0676 62 3 14 0.0100 15 0 15 0.0667 63 3 15 0.0093
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 34 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.9.3.2 calculating the relative source resistance the reference source resistance r s(ref) can be calculated using equation 6 . (6) the reference source resistance (r s(ref) ) during the modulation phase can be calculated using modconductance registers gscfgmod[5:0]. 9.9.3.3 calculating the effective source resistance wiring resistance (r s(wire) ): wiring and bonding add a constant offset to the driver resistance that is relevant when pins tx1 and tx2 are switched to low-impedance. the additional resistance for pin tx1 (r s(wire)tx1 ) can be set approximately as shown in equation 7 . (7) effective resistance (r sx ): the source resistances of the driver transistors (rsmaxp byte) read from the product information field (see section 9.2.1 on page 13 ) are measured during the production test with cwconductance registers gscfgcw[5:0] = 01h. to calculate the driver resistance for a speci?c value set in gscfgmod[5:0], use equation 8 . (8) 9.9.4 pulse width the envelope carries the data signal information that is transmitted to the card. it is an encoded data signal based on the miller code. in addition, each pause of the miller encoded signal is again encoded as a pulse of a ?xed width. the width of the pulse is adjusted using the modwidth register. the pulse width (t w ) is calculated using equation 9 where the frequency constant (f clk ) = 13.56 mhz. (9) 9.10 receiver circuitry the clrc632 uses an integrated quadrature demodulation circuit enabling it to detect an iso/iec 14443 a or iso/iec 14443 b compliant subcarrier signal on pin rx. ? iso/iec 14443 a subcarrier signal: de?ned as a manchester coded ask modulated signal ? iso/iec 14443 b subcarrier signal: de?ned as an nrz-l coded bpsk modulated iso/iec 14443 b subcarrier signal r sref () 1 mant gscfgcw 77 40 ----- - ? ?? exp gscfgcw --------------------------------------------------------------------------------- = r s wire () tx1 500 m w ? r sx r sref () maxp r s wire () tx1 C () r srel () r swire () tx1 + = t w 2 modwidth 1 + f c ------------------------------------ - =
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 35 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) the quadrature demodulator uses two different clocks (q-clock and i-clock) with a phase-shift of 90 between them. both resulting subcarrier signals are ampli?ed, ?ltered and forwarded to the correlation circuitry. the correlation results are evaluated, digitized and then passed to the digital circuitry. various adjustments can be made to obtain optimum performance for all processing units. 9.10.1 receiver circuit block diagram figure 12 shows the block diagram of the receiver circuit. the receiving process can be broken down in to several steps. quadrature demodulation of the 13.56 mhz carrier signal is performed. to achieve the optimum performance, automatic q-clock calibration is recommended (see section 9.10.2.1 on page 35 ). the demodulated signal is ampli?ed by an adjustable ampli?er. a correlation circuit calculates the degree of similarity between the expected and the received signal. the bitphase register enables correlation interval position alignment with the received signals bit grid. in the evaluation and digitizer circuitry, the valid bits are detected and the digital results are sent to the fifo buffer. several tuning steps are possible for this circuit. the signal can be observed on its way through the receiver as shown in figure 12 . one signal at a time can be routed to pin aux using the testanaselect register as described in section 15.2.2 on page 112 . 9.10.2 receiver operation in general, the default settings programmed in the startup initialization ?le are suitable for use with the clrc632 to mifare card data communication. however, in some environments speci?c user settings will achieve better performance. 9.10.2.1 automatic q-clock calibration the quadrature demodulation concept of the receiver generates a phase signal (i-clock) anda90 phase-shifted quadrature signal (q-clock). to achieve the optimum demodulator performance, the q-clock and the i-clock must be phase-shifted by 90 . after the reset phase, a calibration procedure is automatically performed. fig 12. receiver circuit block diagram 001aak615 clkqdelay[4:0] clkqcalib clkq180deg bitphase[7:0] correlation circuitry evaluation and digitizer circuitry minlevel[3:0] colllevel[3:0] rxwait[7:0] rcvclksell s_valid s_data s_coll s_clock gain[1:0] to testanaoutsel clock i to q conversion i-clock q-clock 13.56 mhz demodulator rx vcorrdi vcorrni vcorrdq vcorrnq vevalr vevall vrxfollq vrxfolli vrxampi vrxampq
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 36 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) automatic calibration can be set-up to execute at the end of each transceive command if bit clkqcalib = logic 0. setting bit clkqcalib = logic 1 disables all automatic calibrations except after the reset sequence. automatic calibration can also be triggered by the software when bit clkqcalib has a logic 0 to logic 1 transition. remark: the duration of the automatic q-clock calibration is 65 oscillator periods or approximately 4.8 m s. the clockqcontrol registers clkqdelay[4:0] value is proportional to the phase-shift between the q-clock and the i-clock. the clkq180deg status ?ag bit is set when the phase-shift between the q-clock and the i-clock is greater than 180 . remark: ? the startup con?guration ?le enables automatic q-clock calibration after a reset ? if bit clkqcalib = logic 1, automatic calibration is not performed. leaving this bit set to logic 1 can be used to permanently disable automatic calibration. ? it is possible to write data to the clkqdelay[4:0] bits using the microprocessor. the aim could be to disable automatic calibration and set the delay using the software. con?guring the delay value using the software requires bit clkqcalib to have been previously set to logic 1 and a time interval of at least 4.8 m s has elapsed. each delay value must be written with bit clkqcalib set to logic 1. if bit clkqcalib is logic 0, the con?gured delay value is overwritten by the next automatic calibration interval. 9.10.2.2 ampli?er the demodulated signal must be ampli?ed by the variable ampli?er to achieve the best performance. the gain of the ampli?ers can be adjusted using the rxcontrol1 register gain[1:0] bits; see t ab le 29 . fig 13. automatic q-clock calibration 001aak616 calibration impulse from reset sequence a rising edge initiates q-clock calibration clkqcalib bit calibration impulse from end of transceive command table 29. gain factors for the internal ampli?er see t ab le 86 rxcontrol1 register bit descr iptions on page 64 for additional information. register setting gain factor [db] (simulation results) 00 20 01 24 10 31 11 35
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 37 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.10.2.3 correlation circuitry the correlation circuitry calculates the degree of matching between the received and an expected signal. the output is a measure of the amplitude of the expected signal in the received signal. this is done for both, the q and i-channels. the correlator provides two outputs for each of the two input channels, resulting in a total of four output signals. the correlation circuitry needs the phase information for the incoming card signal for optimum performance. this information is de?ned for the microprocessor using the bitphase register. this value de?nes the phase relationship between the transmitter and receiver clock in multiples of the bitphase time (t bitphase )=1/ 13.56 mhz. 9.10.2.4 evaluation and digitizer circuitry the correlation results are evaluated for each bit-half of the manchester coded signal. the evaluation and digitizer circuit decides from the signal strengths of both bit-halves, if the current bit is valid ? if the bit is valid, its value is identi?ed ? if the bit is not valid, it is checked to identify if it contains a bit-collision select the following levels for optimal using rxthreshold register bits: ? minlevel[3:0]: de?nes the minimum signal strength of the stronger bit-halves signal which is considered valid. ? colllevel[3:0]: de?nes the minimum signal strength relative to the amplitude of the stronger half-bit that has to be exceeded by the weaker half-bit of the manchester coded signal to generate a bit-collision. if the signals strength is below this value, logic 1 and logic 0 can be determined unequivocally. after data transmission, the card is not allowed to send its response before a preset time period which is called the frame guard time in the iso/iec 14443 standard. the length of this time period is set using the rxwait registers rxwait[7:0] bits. the rxwait register de?nes when the receiver is switched on after data transmission to the card in multiples of one bit duration. if bit rcvclkseli is set to logic 1, the i-clock is used to clock the correlator and evaluation circuits. if bit rcvclkseli is set to logic 0, the q-clock is used. remark: it is recommended to use the q-clock. 9.11 serial signal switch the clrc632 comprises two main blocks: ? digital circuitry: comprising the state machines, encoder and decoder logic etc. ? analog circuitry : comprising the modulator, antenna drivers, receiver and ampli?cation circuitry the interface between these two blocks can be con?gured so that the interface signals are routed to pins mfin and mfout. this makes it possible to connect the analog part of one clrc632 to the digital part of another device. the serial signal switch can be used to measure mifare and iso/iec 14443 a as well as related i-code1 and iso/iec 15693 signals.
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 38 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) remark: pin mfin can only be accessed at 106 kbd based on iso/iec 14443 a. the manchester signal and the manchester signal with subcarrier can only be accessed on pin mfout at 106 kbd based on iso/iec 14443 a. 9.11.1 serial signal switch block diagram figure 14 shows the serial signal switches. three different switches are implemented in the serial signal switch enabling the clrc632 to be used in different con?gurations. the serial signal switch can also be used to check the transmitted and received data during the design-in phase or for test purposes. section 15.2.1 on page 110 describes the analog test signals and measurements at the serial signal switch. remark: the slr400 uses pin name sigout for pin mfout. the clrc632 functionality includes the test modes for the slrc400 using pin mfout. section 9.11.2 , section 9.11.2.1 and section 9.11.2.2 describe the relevant registers and settings used to con?gure and control the serial signal switch. 9.11.2 serial signal switch registers the rxcontrol2 register decodersource[1:0] bits de?ne the input signal for the internal manchester decoder and are described in t ab le 30 . fig 14. serial signal switch block diagram 3 001aak617 mfin mfout modulator driver (part of) analog circuitry subcarrier demodulator tx1 tx2 rx carrier demodulator 2 miller coder 1 out of 256 nrz or 1 out of 4 manchester decoder serial signal switch (part of) serial data processing decoder source[1:0] 2 modulator source[1:0] subcarrier demodulator serial data out 00 1 internal 2 manchester with subcarrier 3 0 1 2 3 4 5 6 0 1 envelope mfin 0 1 2 3 manchester manchester out serial data in 7 0 01 1 envelope transmit nrz manchester with subcarrier manchester reserved reserved mfoutselect[2:0] digital test signal signal to mfout
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 39 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) the txcontrol register modulatorsource[1:0] bits de?ne the signal used to modulate the transmitted 13.56 mhz energy carrier. the modulated signal drives pins tx1 and tx2. the mfoutselect register mfoutselect[2:0] bits select the output signal which is to be routed to pin mfout. to use the mfoutselect[2:0] bits, the testdigiselect register signaltomfout bit must be logic 0. 9.11.2.1 active antenna concept the clrc632 analog and digital circuitry is accessed using pins mfin and mfout. t ab le 33 lists the required settings. table 30. decodersource[1:0] values see t ab le 96 on page 67 for additional information. number decodersource [1:0] input signal to decoder 0 00 constant 0 1 01 output of the analog part. this is the default con?guration 2 10 direct connection to pin mfin; expects an 847.5 khz subcarrier signal modulated by a manchester encoded signal 3 11 direct connection to pin mfin; expects a manchester encoded signal table 31. modulatorsource[1:0] values see t ab le 96 on page 67 for additional information. number modulatorsource [1:0] input signal to modulator 0 00 constant 0 (energy carrier off on pins tx1 and tx2) 1 01 constant 1 (continuous energy carrier on pins tx1 and tx2) 2 10 modulation signal (envelope) from the internal encoder. this is the default con?guration. 3 11 direct connection to mfin; expects a miller pulse coded signal table 32. mfoutselect[2:0] values see t ab le 110 on page 70 for additional information. number mfoutselect [2:0] signal routed to pin mfout 0 000 constant low 1 001 constant high 2 010 modulation signal (envelope) from the internal encoder 3 011 serial data stream to be transmitted; the same as for mfoutselect[2:0] = 001 but not encoded by the selected pulse encoder 4 100 output signal of the receiver circuit; card modulation signal regenerated and delayed 5 101 output signal of the subcarrier demodulator; manchester coded card signal 6 110 reserved 7 111 reserved
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 40 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) [1] the number column refers to the value in the number column of t ab le 30 , t ab le 31 and t ab le 32 . two clrc632 devices con?gured as described in t ab le 33 can be connected to each other using pins mfout and mfin. remark: the active antenna concept can only be used at 106 kbd based on iso/iec 14443 a. 9.11.2.2 driving both rf parts it is possible to connect both passive and active antennas to a single ic. the passive antenna pins tx1, tx2 and rx are connected using the appropriate ?lter and matching circuit. at the same time an active antenna is connected to pins mfout and mfin. in this con?guration, two rf parts can be driven, one after another, by one microprocessor. 9.12 mifare higher baud rates the mifare system is speci?ed with a ?xed baud rate of 106 kbd for communication on the rf interface. the current version of iso/iec 14443 a also de?nes 106 kbd for the initial phase of a communication between proximity integrated circuit cards (picc) and proximity coupling devices (pcd). to cover requirements of large data transmissions and to speed up terminal to card communication, the clrc632 supports communication at mifare higher baud rates in combination with a microcontroller ic such as the mifare prox. the mifare higher baud rates concept is described in the application note: mifare implementation of higher baud rates ref . 5 . this application covers the integration of the mifare higher baud rates communication concept in current applications. table 33. register settings to enable use of the analog circuitry register number [1] signal clrc632 pin analog circuitry settings modulatorsource 3 miller pulse encoded mfin mfoutselect 4 manchester encoded with subcarrier mfout decodersource x - - digital circuitry settings modulatorsource x - - mfoutselect 2 miller pulse encoded mfout decodersource 2 manchester encoded with subcarrier mfin table 34. mifare higher baud rates communication direction baud rates (kbd) clrc632 based pcd ? microcontroller picc supporting higher baud rates 106, 212, 424 microcontroller picc supporting higher baud rates ? clrc632 based pcd 106, 212, 424
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 41 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.13 iso/iec 14443 b communication scheme the international standard iso/iec 14443 covers two communication schemes; iso/iec 14443 a and iso/iec 14443 b. the clrc632 reader ic fully supports both iso/iec 14443 variants. t ab le 35 describes the registers and ?ags covered by the iso/iec 14443 b communication protocol. as reference documentation, the international standard iso/iec 14443 identi?cation cards - contactless integrated circuit(s) cards - proximity cards, part 1-4 ( ref . 4 ) can be used. remark: nxp semiconductors does not offer a basic function library to design-in the iso/iec 14443 b protocol. table 35. iso/iec 14443 b registers and ?ags flag register bit register address charspacing[2:0] typebframing 4 to 2 17h coderrate[2:0] codercontrol 5 to 3 14h eofwidth typebframing 5 17h filterampdet bpskdemcontrol 4 1dh force100ask txcontrol 4 11h gscfgcw[5:0] cwconductance 5 to 0 12h gscfgmod[5:0] modconductance 5 to 0 13h minlevel[3:0] rxthreshold 7 to 4 1ch notxeof typebframing 6 17h notxsof typebframing 7 17h norxegt bpskdemcontrol 6 1dh norxeof bpskdemcontrol 5 1dh norxsof bpskdemcontrol 7 1dh rxcoding decodercontrol 0 1ah rxframing[1:0] decodercontrol 4 to 3 1ah sofwidth[1:0] typebframing 1 to 0 17h subcpulses[2:0] rxcontrol1 7 to 5 19h taub[1:0] bpskdemcontrol 1 to 0 1dh taud[1:0] bpskdemcontrol 3 to 2 1dh txcoding[2:0] codercontrol 2 to 0 14h
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 42 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.14 mifare authentication and crypto1 the security algorithm used in the mifare products is called crypto1. it is based on a proprietary stream cipher with a 48-bit key length. to access data on mifare cards, knowledge of the key format is needed. the correct key must be available in the clrc632 to enable successful card authentication and access to the cards data stored in the eeprom. after a card is selected as de?ned in iso/iec 14443 a standard, the user can continue with the mifare protocol. it is mandatory that card authentication is performed. crypto1 authentication is a 3-pass authentication which is automatically performed when the authent1 and authent2 commands are executed (see section 11.7.3 on page 98 and section 11.7.4 on page 98 ). during the card authentication procedure, the security algorithm is initialized. after a successful authentication, communication with the mifare card is encrypted. 9.14.1 crypto1 key handling on execution of the authentication command, the clrc632 reads the key from the key buffer. the key is always read from the key buffer and ensures crypto1 authentication commands do not require addressing of a key. the user must ensure the correct key is prepared in the key buffer before triggering card authentication. the key buffer can be loaded from: ? the eeprom using the loadkeye2 command (see section 11.7.1 on page 97 ) ? the microprocessors fifo buffer using the loadkey command (see section 11.7.2 on page 97 ). this is shown in figure 15 . fig 15. crypto1 key handling block diagram 001aak624 fifo buffer from the microcontroller writee2 loadkey eeprom keys key buffer loadkeye2 during authent1 crypto1 module serial data stream out serial data stream in (plain) (encrypted)
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 43 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.14.2 authentication procedure the crypto1 security algorithm enables authentication of mifare cards. to obtain valid authentication, the correct key has to be available in the key buffer of the clrc632. this can be ensured as follows: 1. load the internal key buffer by using the loadkeye2 (see section 11.7.1 on page 97 ) or the loadkey (see section 11.7.2 on page 97 ) commands. 2. start the authent1 command (see section 11.7.3 on page 98 ). when ?nished, check the error ?ags to obtain the command execution status. 3. start the authent2 command (see section 11.7.4 on page 98 ). when ?nished, check the error ?ags and bit crypto1on to obtain the command execution status. 10. clrc632 registers 10.1 register addressing modes three methods can be used to operate the clrc632: ? initiating functions and controlling data by executing commands ? con?guring the functional operation using a set of con?guration bits ? monitoring the state of the clrc632 by reading status ?ags the commands, con?guration bits and ?ags are accessed using the microprocessor interface. the clrc632 can internally address 64 registers using six address lines. 10.1.1 page registers the clrc632 register set is segmented into eight pages contain eight registers each. a page register can always be addressed, irrespective of which page is currently selected. 10.1.2 dedicated address bus when using the clrc632 with the dedicated address bus, the microprocessor de?nes three address lines using address pins a0, a1 and a2. this enables addressing within a page. to switch between registers in different pages a paging mechanism needs to be used. t ab le 36 shows how the register address is assembled. 10.1.3 multiplexed address bus the microprocessor may de?ne all six address lines at once using the clrc632 with a multiplexed address bus. in this case either the paging mechanism or linear addressing can be used. t ab le 37 shows how the register address is assembled. table 36. dedicated address bus: assembling the register address register bit: usepageselect register address 1 pageselect2 pageselect1 pageselect0 a2 a1 a0
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 44 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.2 register bit behavior bits and ?ags for different registers behave differently, depending on their functions. in principle, bits with same behavior are grouped in common registers. t ab le 38 describes the function of the access column in the register tables. table 37. multiplexed address bus: assembling the register address multiplexed address bus type usepage select register address paging mode 1 pageselect2 pageselect1 pageselect0 ad2 ad1 ad0 linear addressing 0 ad5 ad4 ad3 ad2 ad1 ad0 table 38. behavior and designation of register bits abbreviation behavior description r/w read and write these bits can be read and written by the microprocessor. since they are only used for control, their content is not in?uenced by internal state machines. example: timerreload register may be read and written by the microprocessor. it will also be read by internal state machines but never changed by them. d dynamic these bits can be read and written by the microprocessor. nevertheless, they may also be written automatically by internal state machines. example: the command register changes its value automatically after the execution of the command. r read only these registers hold ?ags which have a value determined by internal states only. example: the errorflag register cannot be written externally but shows internal states. w write only these registers are used for control only. they may be written by the microprocessor but cannot be read. reading these registers returns an unde?ned value. example: the testanaselect register is used to determine the signal on pin aux however, it is not possible to read its content.
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 45 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.3 register overview table 39. clrc632 register overview sub address (hex) register name function refer to page 0: command and status 00h page selects the page register t ab le 41 on page 50 01h command starts and stops command execution t ab le 43 on page 50 02h fifodata input and output of 64-byte fifo buffer t ab le 45 on page 51 03h primarystatus receiver and transmitter and fifo buffer status ?ags t ab le 47 on page 51 04h fifolength number of bytes buffered in the fifo buffer t ab le 49 on page 52 05h secondarystatus secondary status ?ags t ab le 51 on page 53 06h interrupten enable and disable interrupt request control bits t ab le 53 on page 53 07h interruptrq interrupt request ?ags t ab le 55 on page 54 page 1: control and status 08h page selects the page register t ab le 41 on page 50 09h control control ?ags for timer unit, power saving etc t ab le 57 on page 55 0ah errorflag show the error status of the last command executed t ab le 59 on page 55 0bh collpos bit position of the ?rst bit-collision detected on the rf interface t ab le 61 on page 56 0ch timervalue value of the timer t ab le 63 on page 57 0dh crcresultlsb lsb of the crc coprocessor register t ab le 65 on page 57 0eh crcresultmsb msb of the crc coprocessor register t ab le 67 on page 57 0fh bitframing adjustments for bit oriented frames t ab le 69 on page 58 page 2: transmitter and coder control 10h page selects the page register t ab le 41 on page 50 11h txcontrol controls the operation of the antenna driver pins tx1 and tx2 t ab le 71 on page 59 12h cwconductance selects the conductance of the antenna driver pins tx1 and tx2 t ab le 73 on page 60 13h modconductance de?nes the driver output conductance t ab le 75 on page 60 14h codercontrol sets the clock frequency and the encoding t ab le 77 on page 61 15h modwidth selects the modulation pulse width t ab le 79 on page 62 16h modwidthsof selects the sof pulse-width modulation (i-code1 fast mode) t ab le 81 on page 62 17h typebframing de?nes the framing for iso/iec 14443 b communication t ab le 83 on page 63 page 3: receiver and decoder control 18 page selects the page register t ab le 41 on page 50 19 rxcontrol1 controls receiver behavior t ab le 85 on page 64 1a decodercontrol controls decoder behavior t ab le 87 on page 65 1b bitphase selects the bit-phase between transmitter and receiver clock t ab le 89 on page 65 1c rxthreshold selects thresholds for the bit decoder t ab le 91 on page 66 1d bpskdemcontrol controls bpsk receiver behavior t ab le 93 on page 66 1eh rxcontrol2 controls decoder and de?nes the receiver input source t ab le 95 on page 67 1fh clockqcontrol clock control for the 90 phase-shifted q-channel clock t ab le 97 on page 67
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 46 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.4 clrc632 register ?ags overview page 4: rf timing and channel redundancy 20h page selects the page register t ab le 41 on page 50 21h rxwait selects the interval after transmission before the receiver starts t ab le 99 on page 68 22h channelredundancy selects the method and mode used to check data integrity on the rf channel t ab le 101 on page 68 23h crcpresetlsb preset lsb value for the crc register t ab le 103 on page 69 24h crcpresetmsb preset msb value for the crc register t ab le 105 on page 69 25h timeslotperiod selects the time between automatically transmitted frames t ab le 107 on page 69 26h mfoutselect selects internal signal applied to pin mfout, includes the msb of value timeslotperiod; see t ab le 107 on page 69 t ab le 109 on page 70 27h preset27 these values are not changed t ab le 111 on page 70 page 5: fifo, timer and irq pin con?guration 28h page selects the page register t ab le 41 on page 50 29h fifolevel de?nes the fifo buffer over?ow and under?ow warning levels t ab le 49 on page 52 2ah timerclock selects the timer clock divider t ab le 114 on page 71 2bh timercontrol selects the timer start and stop conditions t ab le 116 on page 72 2ch timerreload de?nes the timer preset value t ab le 118 on page 72 2dh irqpincon?g con?gures pin irq output stage t ab le 120 on page 73 2eh preset2e these values are not changed t ab le 122 on page 73 2fh preset2f these values are not changed t ab le 123 on page 73 page 6: reserved registers 30h page selects the page register t ab le 41 on page 50 31h reserved reserved t ab le 124 on page 73 32h reserved reserved 33h reserved reserved 34h reserved reserved 35h reserved reserved 36h reserved reserved 37h reserved reserved page 7: test control 38h page selects the page register t ab le 41 on page 50 39h reserved reserved t ab le 125 on page 74 3ah testanaselect selects analog test mode t ab le 126 on page 74 3bh reserved reserved t ab le 128 on page 75 3ch reserved reserved t ab le 129 on page 75 3dh testdigiselect selects digital test mode t ab le 130 on page 75 3eh reserved reserved t ab le 132 on page 76 3fh reserved reserved table 39. clrc632 register overview continued sub address (hex) register name function refer to
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 47 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) table 40. clrc632 register ?ags overview flag(s) register bit address accesserr errorflag 5 0ah bitphase[7:0] bitphase 7 to 0 1bh charspacing[2:0] typebframing 4 to 2 17h, clkq180deg clockqcontrol 7 1fh clkqcalib clockqcontrol 6 1fh clkqdelay[4:0] clockqcontrol 4 to 0 1fh coderrate[2:0] codercontrol 5 to 3 14h collerr errorflag 0 0ah colllevel[3:0] rxthreshold 3 to 0 1ch collpos[7:0] collpos 7 to 0 0bh command[5:0] command 5 to 0 01h crc3309 channelredundancy 5 22h crc8 channelredundancy 4 22h crcerr errorflag 3 0ah crcpresetlsb[7:0] crcpresetlsb 7 to 0 23h crcpresetmsb[7:0] crcpresetmsb 7 to 0 24h crcready secondarystatus 5 05h crcresultmsb[7:0] crcresultmsb 7 to 0 0eh crcresultlsb[7:0] crcresultlsb 7 to 0 0dh crypto1on control 3 09h decodersource[1:0] rxcontrol2 1 to 0 1eh e2ready secondarystatus 6 05h eofwidth typebframing 5 17h err primarystatus 2 03h fifodata[7:0] fifodata 7 to 0 02h fifolength[6:0] fifolength 6 to 0 04h fifoov? errorflag 4 0ah filterampdet bpskdemcontrol 4 1dh flushfifo control 0 09h force100ask txcontrol 4 11h framingerr errorflag 2 0ah gain[1:0] rxcontrol1 1 to 0 19h gscfgcw[5:0] cwconductance 5 to 0 12h gscfgmod[5:0] modconductance 5 to 0 13h hialert primarystatus 1 03h hialertien interrupten 1 06h hialertirq interruptrq 1 07h idleien interrupten 2 06h idleirq interruptrq 2 07h ifdetectbusy command 7 01h irq primarystatus 3 03h
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 48 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) irqinv irqpincon?g 1 2dh irqpushpull irqpincon?g 0 2dh iso selection[1:0] rxcontrol1 4 to 3 19h keyerr errorflag 6 0ah loalert primarystatus 0 03h loalertien interrupten 0 06h loalertirq interruptrq 0 07h lpoff rxcontrol1 2 19h mfoutselect[2:0] mfoutselect 2 to 0 26h minlevel[3:0] rxthreshold 7 to 4 1ch modemstate[2:0] primarystatus 6 to 4 03h modulatorsource[1:0] txcontrol 6 to 5 11h modwidth[7:0] modwidth 7 to 0 15h norxegt bpskdemcontrol 6 1dh norxeof bpskdemcontrol 5 1dh norxsof bpskdemcontrol 7 1dh notxeof typebframing 6 17h notxsof typebframing 7 17h pageselect[2:0] page 2 to 0 00h, 08h, 10h, 18h, 20h, 28h, 30h and 38h parityen channelredundancy 0 22h parityerr errorflag 1 0ah parityodd channelredundancy 1 22h powerdown control 4 09h rcvclkseli rxcontrol2 7 1eh rxalign[2:0] bitframing 6 to 4 0fh rxautopd rxcontrol2 6 1eh rxcrcen channelredundancy 3 22h rxcoding decodercontrol 0 1ah rxframing[1:0] decodercontrol 4 to 3 1ah rxien interrupten 3 06h rxirq interruptrq 3 07h rxlastbits[2:0] secondarystatus 2 to 0 05h rxmultiple decodercontrol 6 1ah rxwait[7:0] rxwait 7 to 0 21h setien interrupten 7 06h setirq interruptrq 7 07h signaltomfout testdigiselect 7 3dh sofwidth[1:0] typebframing 1 to 0 17h standby control 5 09h subcpulses[2:0] rxcontrol1 7 to 5 19h table 40. clrc632 register ?ags overview continued flag(s) register bit address
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 49 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) taub[1:0] bpskdemcontrol 1 to 0 1dh taud[1:0] bpskdemcontrol 3 to 2 1dh tautorestart timerclock 5 2ah testanaoutsel[4:0] testanaselect 3 to 0 3ah testdigisignalsel[6:0] testdigiselect 6 to 0 3dh timerien interrupten 5 06h timerirq interruptrq 5 07h timervalue[7:0] timervalue 7 to 0 0ch timeslotperiod[7:0] timeslotperiod 7 to 0 25h timeslotperiodmsb mfoutselect 4 26h tprescaler[4:0] timerclock 4 to 0 2ah treloadvalue[7:0] timerreload 7 to 0 2ch trunning secondarystatus 7 05h tstarttxbegin timercontrol 0 2bh tstarttxend timercontrol 1 2bh tstartnow control 1 09h tstoprxbegin timercontrol 2 2bh tstoprxend timercontrol 3 2bh tstopnow control 2 09h tx1rfen txcontrol 0 11h tx2cw txcontrol 3 11h tx2inv txcontrol 3 11h tx2rfen txcontrol 1 11h txcoding[2:0] codercontrol 2 to 0 14h txcrcen channelredundancy 2 22h txien interrupten 4 06h txirq interruptrq 4 07h txlastbits[2:0] bitframing 2 to 0 0fh usepageselect page 7 00h, 08h, 10h, 18h, 20h, 28h, 30h and 38h waterlevel[5:0] fifolevel 5 to 0 29h zeroaftercoll decodercontrol 7 1ah, bit 5 table 40. clrc632 register ?ags overview continued flag(s) register bit address
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 50 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5 register descriptions 10.5.1 page 0: command and status 10.5.1.1 page register selects the page register. 10.5.1.2 command register starts and stops the command execution. table 41. page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h) reset value: 1000 0000b, 80h bit allocation bit 7 6 5 4 3 2 1 0 symbol usepageselect 0000 pageselect[2:0] access r/w r/w r/w r/w r/w table 42. page register bit descriptions bit symbol value description 7 usepageselect 1 the value of pageselect[2:0] is used as the register address a5, a4, and a3. the lsbs of the register address are de?ned using the address pins or the internal address latch, respectively. 0 the complete content of the internal address latch de?nes the register address. the address pins are used as described in t ab le 5 on page 8 . 6 to 3 0000 - reserved 2 to 0 pageselect[2:0] - when usepageselect = logic 1, the value of pageselect is used to specify the register page (a5, a4 and a3 of the register address) table 43. command register (address: 01h) reset value: x000 0000b, x0h bit allocation bit 7 6 5 4 3 2 1 0 symbol ifdetectbusy 0 command[5:0] access r r d table 44. command register bit descriptions bit symbol value description 7 ifdetectbusy - shows the status of interface detection logic 0 interface detection ?nished successfully 1 interface detection ongoing 6 0 - reserved 5 to 0 command[5:0] - activates a command based on the command code. reading this register shows which command is being executed.
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 51 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.1.3 fifodata register input and output of the 64 byte fifo buffer. 10.5.1.4 primarystatus register bits relating to receiver, transmitter and fifo buffer status ?ags. table 45. fifodata register (address: 02h) reset value: xxxx xxxxb, 05h bit allocation bit 7 6 5 4 3 2 1 0 symbol fifodata[7:0] access d table 46. fifodata register bit descriptions bit symbol description 7 to 0 fifodata[7:0] data input and output port for the internal 64-byte fifo buffer. the fifo buffer acts as a parallel in to parallel out converter for all data streams. table 47. primarystatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0 modemstate[2:0] irq err hialert loalert access r r r r r r table 48. primarystatus register bit descriptions bit symbol value status description 7 0 - reserved 6 to 4 modemstate[2:0] shows the state of the transmitter and receiver state machines: 000 idle neither the transmitter or receiver are operating; neither of them are started or have input data 001 txsof transmit start of frame pattern 010 txdata transmit data from the fifo buffer (or redundancy crc check bits) 011 txeof transmit end of frame (eof) pattern 100 gotorx1 intermediate state 1; receiver starts gotorx2 intermediate state 2; receiver ?nishes 101 preparerx waiting until the rxwait register time period expires 110 awaitingrx receiver activated; waiting for an input signal on pin rx 111 receiving receiving data 3 irq - shows any interrupt source requesting attention based on the interrupten register ?ag settings
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 52 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.1.5 fifolength register number of bytes in the fifo buffer. 2 err 1 any error ?ag in the errorflag register is set 1 hialert 1 the alert level for the number of bytes in the fifo buffer (fifolength[6:0]) is: otherwise value = logic 0 example: fifolength = 60, waterlevel = 4 then hialert = logic 1 fifolength = 59, waterlevel = 4 then hialert = logic 0 0 loalert 1 the alert level for number of bytes in the fifo buffer (fifolength[6:0]) is: otherwise value = logic 0 example: fifolength = 4, waterlevel = 4 then loalert = logic 1 fifolength = 5, waterlevel = 4 then loalert = logic 0 table 48. primarystatus register bit descriptions continued bit symbol value status description hialert 64 fifolength C () waterlevel = loalert fifolength waterlevel = table 49. fifolength register (address: 04h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0 fifolength[6:0] access r r table 50. fifolength bit descriptions bit symbol description 7 0 reserved 6 to 0 fifolength[6:0] gives the number of bytes stored in the fifo buffer. writing increments the fifolength register value while reading decrements the fifolength register value
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 53 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.1.6 secondarystatus register various secondary status ?ags. 10.5.1.7 interrupten register control bits to enable and disable passing of interrupt requests. [1] this bit can only be set or cleared using bit setien. table 51. secondarystatus register (address: 05h) reset value: 01100 000b, 60h bit allocation bit 7 6 5 4 3 2 1 0 symbol trunning e2ready crcready 00 rxlastbits[2:0] access r r r r r table 52. secondarystatus register bit descriptions bit symbol value description 7 trunning 1 the timer unit is running and the counter decrements the timervalue register on the next timer clock cycle 0 the timer unit is not running 6 e2ready 1 eeprom programming is ?nished 0 eeprom programming is ongoing 5 crcready 1 crc calculation is ?nished 0 crc calculation is ongoing 4 to 3 00 - reserved 2 to 0 rxlastbits [2:0] - shows the number of valid bits in the last received byte. if zero, the whole byte is valid table 53. interrupten register (address: 06h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol setien 0 timerien txien rxien idleien hialertien loalertien access w r/w r/w r/w r/w r/w r/w r/w table 54. interrupten register bit descriptions bit symbol value description 7 setien 1 indicates that the marked bits in the interrupten register are set 0 clears the marked bits 6 0 - reserved 5 timerien - sends the timerirq timer interrupt request to pin irq [1] 4 txien - sends the txirq transmitter interrupt request to pin irq [1] 3 rxien - sends the rxirq receiver interrupt request to pin irq [1] 2 idleien - sends the idleirq idle interrupt request to pin irq [1] 1 hialertien - sends the hialertirq high alert interrupt request to pin irq [1] 0 loalertien - sends the loalertirq low alert interrupt request to pin irq [1]
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 54 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.1.8 interruptrq register interrupt request ?ags. [1] primarystatus register bit hialertirq stores this event and it can only be reset using bit setirq. table 55. interruptrq register (address: 07h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol setirq 0 timerirq txirq rxirq idleirq hialertirq loalertirq access w r/w d d d d d d table 56. interruptrq register bit descriptions bit symbol value description 7 setirq 1 sets the marked bits in the interruptrq register 0 clears the marked bits in the interruptrq register 6 0 - reserved 5 timerirq 1 timer decrements the timervalue register to zero 0 timer decrements are still greater than zero 4 txirq 1 txirq is set to logic 1 if one of the following events occurs: transceive command; all data transmitted authent1 and authent2 commands; all data transmitted writee2 command; all data is programmed calccrc command; all data is processed 0 when not acted on by transceive, authent1, authent2, writee2 or calccrc commands 3 rxirq 1 the receiver terminates 0 reception still ongoing 2 idleirq 1 command terminates correctly. for example; when the command register changes its value from any command to the idle command. if an unknown command is started the idleirq bit is set. microprocessor start-up of the idle command does not set the idleirq bit. 0 idleirq = logic 0 in all other instances 1 hialertirq 1 primarystatus register hialert bit is set [1] 0 primarystatus register hialert bit is not set 0 loalertirq 1 primarystatus register loalert bit is set [1] 0 primarystatus register loalert bit is not set
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 55 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.2 page 1: control and status 10.5.2.1 page register selects the page register; see section 10.5.1.1 p age register on page 50 . 10.5.2.2 control register various control ?ags, for timer, power saving, etc. 10.5.2.3 errorflag register error ?ags show the error status of the last executed command. table 57. control register (address: 09h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 00 standby powerdown crypto1on tstopnow tstartnow flushfifo access r/w d d d d d d table 58. control register bit descriptions bit symbol value description 7 to 6 00 - reserved 5 standby 1 activates standby mode. the current consuming blocks are switched off but the clock keeps running 4 powerdown 1 activates power-down mode. the current consuming blocks are switched off including the clock 3 crypto1on 1 crypto1 unit is switched on and all data communication with the card is encrypted. this bit can only be set to logic 1 by successful execution of the authent2 command 0 crypto1 unit is switched off. all data communication with the card is unencrypted (plain) 2 tstopnow 1 immediately stops the timer. reading this bit always returns logic 0 1 tstartnow 1 immediately starts the timer. reading this bit will always returns logic 0 0 flushfifo 1 immediately clears the internal fifo buffers read and write pointer, the fifolength[6:0] bits are set to logic 0 and the fifoov? ?ag. reading this bit always returns logic 0 table 59. errorflag register (address: 0ah) reset value: 0100 0000b, 40h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0 keyerr accesserr fifoov? crcerr framingerr parityerr collerr access r r r r r r r r table 60. errorflag register bit descriptions bit symbol value description 7 0 - reserved 6 keyerr 1 set when the loadkeye2 or loadkey command recognize that the input data is not encoded based on the key format de?nition 0 set when the loadkeye2 or the loadkey command starts
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 56 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) [1] only valid for communication using iso/iec 14443 a. 10.5.2.4 collpos register bit position of the ?rst bit-collision detected on the rf interface. remark: a bit collision is not indicated in the collpos register when using the iso/iec 14443 b protocol standard. 5 accesserr 1 set when the access rights to the eeprom are violated 0 set when an eeprom related command starts 4 fifoov? 1 set when the microprocessor or clrc632 internal state machine (e.g. receiver) tries to write data to the fifo buffer when it is full 3 crcerr 1 set when rxcrcen is set and the crc fails 0 automatically set during the preparerx state in the receiver start phase 2 framingerr 1 set when the sof is incorrect 0 automatically set during the preparerx state in the receiver start phase 1 parityerr 1 set when the parity check fails 0 automatically set during the preparerx state in the receiver start phase 0 collerr 1 set when a bit-collision is detected [1] 0 automatically set during the preparerx state in the receiver start phase [1] table 60. errorflag register bit descriptions continued bit symbol value description table 61. collpos register (address: 0bh) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol collpos[7:0] access r table 62. collpos register bit descriptions bit symbol description 7 to 0 collpos[7:0] this register shows the bit position of the ?rst detected collision in a received frame. example: 00h indicates a bit collision in the start bit 01h indicates a bit collision in the 1 st bit ... 08h indicates a bit collision in the 8 th bit
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 57 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.2.5 timervalue register value of the timer. 10.5.2.6 crcresultlsb register lsb of the crc coprocessor register. 10.5.2.7 crcresultmsb register msb of the crc coprocessor register. table 63. timervalue register (address: 0ch) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol timervalue[7:0] access r table 64. timervalue register bit descriptions bit symbol description 7 to 0 timervalue[7:0] this register shows the timer counter value table 65. crcresultlsb register (address: 0dh) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol crcresultlsb[7:0] access r table 66. crcresultlsb register bit descriptions bit symbol description 7 to 0 crcresultlsb[7:0] gives the crc registers least signi?cant byte value; only valid if crcready = logic 1 table 67. crcresultmsb register (address: 0eh) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol crcresultmsb[7:0] access r table 68. crcresultmsb register bit descriptions bit symbol description 7 to 0 crcresultmsb[7:0] gives the crc registers most signi?cant byte value; only valid if crcready = logic 1. the registers value is unde?ned for 8-bit crc calculation.
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 58 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.2.8 bitframing register adjustments for bit oriented frames. table 69. bitframing register (address: 0fh) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0 rxalign[2:0] 0 txlastbits[2:0] access r/w d r/w d table 70. bitframing register bit descriptions bit symbol value description 7 0 - reserved 6 to 4 rxalign[2:0] de?nes the bit position for the ?rst bit received to be stored in the fifo buffer. additional received bits are stored in the next subsequent bit positions. after reception, rxalign[2:0] is automatically cleared. for example: 000 the lsb of the received bit is stored in bit position 0 and the second received bit is stored in bit position 1 001 the lsb of the received bit is stored in bit position 1, the second received bit is stored in bit position 2 ... 111 the lsb of the received bit is stored in bit position 7, the second received bit is stored in the next byte in bit position 0 3 0 - reserved 2 to 0 txlastbits[2:0] - de?nes the number of bits of the last byte that shall be transmitted. 000 indicates that all bits of the last byte will be transmitted. txlastbits[2:0] is automatically cleared after transmission.
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 59 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.3 page 2: transmitter and control 10.5.3.1 page register selects the page register; see section 10.5.1.1 p age register on page 50 . 10.5.3.2 txcontrol register controls the logical behavior of the antenna pin tx1 and tx2. table 71. txcontrol register (address: 11h) reset value: 0101 1000b, 58h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0 modulatorsource [1:0] force 100ask tx2inv tx2cw tx2rfen tx1rfen access r/w r/w r/w r/w r/w r/w r/w table 72. txcontrol register bit descriptions bit symbol value description 7 0 - this value must not be changed 6 to 5 modulatorsource[1:0] selects the source for the modulator input: 00 modulator input is low 01 modulator input is high 10 modulator input is the internal encoder 11 modulator input is pin mfin 4 force100ask - forces a 100 % ask modulation independent modconductance register setting 3 tx2inv 0 delivers an inverted 13.56 mhz energy carrier output signal on pin tx2 2 tx2cw 1 delivers a continuously unmodulated 13.56 mhz energy carrier output signal on pin tx2 0 enables modulation of the 13.56 mhz energy carrier 1 tx2rfen 1 the output signal on pin tx2 is the 13.56 mhz energy carrier modulated by the transmission data 0 tx2 is driven at a constant output level 0 tx1rfen 1 the output signal on pin tx1 is the 13.56 mhz energy carrier modulated by the transmission data 0 tx1 is driven at a constant output level
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 60 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.3.3 cwconductance register selects the conductance of the antenna driver pins tx1 and tx2. see section 9.9.3 on page 32 for detailed information about gscfgcw[5:0]. 10.5.3.4 modconductance register de?nes the driver output conductance. remark: when force100ask = logic 1, the gscfgmod[5:0] value has no effect. see section 9.9.3 on page 32 for detailed information about gscfgmod[5:0]. table 73. cwconductance register (address: 12h) reset value: 0011 1111b, 3fh bit allocation bit 7 6 5 4 3 2 1 0 symbol 00 gscfgcw[5:0] access r/w r/w r/w table 74. cwconductance register bit descriptions bit symbol description 7 to 6 00 these values must not be changed 5 to 0 gscfgcw[5:0] de?nes the conductance register value for the output driver. this can be used to regulate the output power/current consumption and operating distance. table 75. modconductance register (address: 13h) reset value: 0011 1111b, 3fh bit allocation bit 7 6 5 4 3 2 1 0 symbol 00 gscfgmod[5:0] access r/w r/w r/w table 76. modconductance register bit descriptions bit symbol description 7 to 6 00 these values must not be changed 5 to 0 gscfgmod[5:0] de?nes the modconductance register value for the output driver during modulation. this is used to regulate the modulation index.
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 61 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.3.5 codercontrol register sets the clock rate and the coding mode. table 77. codercontrol register (address: 14h) reset value: 0001 1001b, 19h bit allocation bit 7 6 5 4 3 2 1 0 symbol sendonepulse 0 coderrate[2:0] txcoding[2:0] access r/w r/w r/w r/w table 78. codercontrol register bit descriptions bit symbol value description 7 sendonepulse 1 forced iso/iec 15693 modulation. this is used to switch to the next timeslot if the inventory command is used. 0 this bit is not cleared automatically, it must be reset by the user to logic 0 6 0 - this value must not be changed 5 to 3 coderrate[2:0] this register de?nes the clock rate for the encoder circuit 000 mifare 848 kbd 001 mifare 424 kbd 010 mifare 212 kbd 011 mifare 106 kbd; iso/iec 14443 a 100 iso/iec 14443 b 101 i-code1 standard mode and iso/iec 15693 (~52.97 khz) 110 i-code1 fast mode (~26.48 khz) 111 reserved 2 to 0 txcoding[2:0] this register de?nes the bit coding mode and framing during transmission 000 nrz according to iso/iec 14443 b 001 mifare, iso/iec 14443 a, (miller coded) 010 reserved 011 reserved 100 i-code1 standard mode (1 out of 256 coding) 101 i-code1 fast mode (nrz coding) 110 iso/iec 15693 standard mode (1 out of 256 coding) 111 iso/iec 15693 fast mode (1 out of 4 coding)
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 62 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.3.6 modwidth register selects the pulse-modulation width. 10.5.3.7 modwidthsof register table 79. modwidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation bit 7 6 5 4 3 2 1 0 symbol modwidth[7:0] access r/w table 80. modwidth register bit descriptions bit symbol description 7 to 0 modwidth[7:0] de?nes the width of the modulation pulse based on t mod =2 (modwidth + 1) / f clk table 81. modwidthsof register (address: 16h) reset value: 0011 1111b, 3fh bit allocation bit 7 6 5 4 3 2 1 0 symbol modwidthsof[7:0] access r/w table 82. modwidthsof register bit descriptions bit symbol value description 7 to 0 modwidthsof de?nes the width of the modulation pulse for sof as t mod =2 (modwidth + 1) / f clk the register settings are: 3fh mifare and iso/iec 14443; modulation width sof = 9.44 m s 3fh i-code1 standard mode; modulation width sof = 9.44 m s 73h i-code1 fast mode; modulation width sof = 18.88 m s 3fh iso/iec 15693; modulation width sof = 9.44 m s
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 63 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.3.8 typebframing de?nes the framing for iso/iec 14443 b communication. table 83. typebframing register (address: 17h) reset value: 0011 1011b, 3bh bit allocation bit 7 6 5 4 3 2 1 0 symbol notxsof notxeof eofwidth charspacing[2:0] sofwidth[1:0] access r/w r/w r/w r/w r/w table 84. typebframing register bit descriptions bit symbol value description 7 notxsof 1 txcoder suppresses the sof 0 txcoder does not suppress sof 6 notxeof 1 txcoder suppresses the eof 0 txcoder does not suppress the eof 5 eofwidth 1 set the eof to a length to 11 etu 0 set the eof to a length of 10 etu 4 to 2 charspacing[2:0] set the egt length between 0 and 7 etu 1 to 0 sofwidth[1:0] 00 sets the sof to a length to 10 etu low and 2 etu high 01 sets the sof to a length of 10 etu low and 3 etu high 10 sets the sof to a length of 11 etu low and 2 etu high 11 sets the sof to a length of 11 etu low and 3 etu high
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 64 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.4 page 3: receiver and decoder control 10.5.4.1 page register selects the page register; see section 10.5.1.1 p age register on page 50 . 10.5.4.2 rxcontrol1 register controls receiver operation. table 85. rxcontrol1 register (address: 19h) reset value: 0111 0011b, 73h bit allocation bit 7 6 5 4 3 2 1 0 symbol subcpulses[2:0] isoselection[1:0] lpoff gain[1:0] access r/w r/w r/w r/w table 86. rxcontrol1 register bit descriptions bit symbol value description 7 to 5 subcpulses[2:0] de?nes the number of subcarrier pulses for each bit 000 1 pulse for each bit 001 2 pulses for each bit 010 4 pulses for each bit 011 8 pulses for each bit iso/iec 14443 a and iso/iec 14443 b 100 16 pulses for each bit i-code1, iso/iec 15693 101 reserved 110 reserved 111 reserved 4 to 3 isoselection[1:0] used to select the communication protocol 00 reserved 10 iso/iec 14443 a and iso/iec 14443 b 01 i-code1, iso/iec 15693 11 reserved 2 lpoff switches off a low-pass ?lter at the internal ampli?er 1 to 0 gain[1:0] de?nes the receivers signal voltage gain factor 00 20 db gain factor 01 24 db gain factor 10 31 db gain factor 11 35 db gain factor
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 65 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.4.3 decodercontrol register controls decoder operation. 10.5.4.4 bitphase register selects the bit-phase between transmitter and receiver clock. table 87. decodercontrol register (address: 1ah) reset value: 0000 1000b, 08h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0 rxmultiple zeroaftercoll rxframing[1:0] rxinvert 0 rxcoding access r/w r/w r/w r/w r/w r/w r/w table 88. decodercontrol register bit descriptions bit symbol value description 7 0 - this value must not be changed 6 rxmultiple 0 after receiving one frame, the receiver is deactivated 1 enables reception of more than one frame 5 zeroaftercoll 1 any bits received after a bit-collision are masked to zero. this helps to resolve the anti-collision procedure as de?ned in iso/iec 14443 a 4 to 3 rxframing[1:0] 00 i-code1 01 mifare or iso/iec 14443 a 10 iso/iec 15693 11 iso/iec 14443 b 2 rxinvert 0 modulation at the ?rst half-bit results in logic 1 (i-code1) 1 modulation at the ?rst half-bit results in logic 0 (iso/iec 15693) 1 0 - this value must not be changed 0 rxcoding 0 manchester encoding 1 bpsk encoding table 89. bitphase register (address: 1bh) reset value: 1010 1101b, adh bit allocation bit 7 6 5 4 3 2 1 0 symbol bitphase[7:0] access r/w table 90. bitphase register bit descriptions bit symbol description 7 to 0 bitphase de?nes the phase relationship between transmitter and receiver clock remark: the correct value of this register is essential for proper operation.
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 66 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.4.5 rxthreshold register selects thresholds for the bit decoder. 10.5.4.6 bpskdemcontrol controls bpsk demodulation. table 91. rxthreshold register (address: 1ch) reset value: 1111 1111b, ffh bit allocation bit 7 6 5 4 3 2 1 0 symbol minlevel[3:0] colllevel[3:0] access r/w r/w table 92. rxthreshold register bit descriptions bit symbol description 7 to 4 minlevel[3:0] the minimum signal strength the decoder will accept. if the signal strength is below this level, it is not evaluated. 3 to 0 colllevel[3:0] the minimum signal strength the decoder input that must be reached by the weaker half-bit of the manchester encoded signal to generate a bit-collision (relative to the amplitude of the stronger half-bit) table 93. bpskdemcontrol register (address: 1dh) reset value: 0001 1110b, 1eh bit allocation bit 7 6 5 4 3 2 1 0 symbol norxsof norxegt norxeof filterampdet taud[1:0] taub[1:0] access r/w r/w r/w r/w r/w r/w table 94. bpskdemcontrol register bit descriptions bit symbol value description 7 norxsof 1 a missing sof in the received data stream is ignored and no framing errors are indicated 0 a missing sof in the received data stream generates framing errors 6 norxegt 1 an egt which is too short or too long in the received data stream is ignored and no framing errors are indicated 0 an egt which is too short or too long in the received data stream will cause framing errors 5 norxeof 1 a missing eof in the received data stream is ignored and no framing errors indicated 0 a missing eof in the receiving data stream produces framing errors 4 filterampdet - switches on a high-pass ?lter for amplitude detection 3 to 2 taud[1:0] - changes the time constant of the internal pll whilst receiving data 1 to 0 taub[1:0] - changes the time constant of the internal pll during data bursts
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 67 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.4.7 rxcontrol2 register controls decoder behavior and de?nes the input source for the receiver. [1] i-clock and q-clock are 90 phase-shifted from each other. 10.5.4.8 clockqcontrol register controls clock generation for the 90 phase-shifted q-clock. table 95. rxcontrol2 register (address: 1eh) reset value: 0100 0001b, 41h bit allocation bit 7 6 5 4 3 2 1 0 symbol rcvclkseli rxautopd 0000 decodersource[1:0] access r/w r/w r/w r/w table 96. rxcontrol2 register bit descriptions bit symbol value description 7 rcvclkseli 1 i-clock is used as the receiver clock [1] 0 q-clock is used as the receiver clock [1] 6 rxautopd 1 receiver circuit is automatically switched on before receiving and switched off afterwards. this can be used to reduce current consumption. 0 receiver is always activated 5 to 2 0000 - these values must not be changed 1 to 0 decodersource[1:0] selects the source for the decoder input 00 low 01 internal demodulator 10 a subcarrier modulated manchester encoded signal on pin mfin 11 a baseband manchester encoded signal on pin mfin table 97. clockqcontrol register (address: 1fh) reset value: 000x xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol clkq180deg clkqcalib 0 clkqdelay[4:0] access r r/w r/w d table 98. clockqcontrol register bit descriptions bit symbol value description 7 clkq180deg 1 q-clock is phase-shifted more than 180 compared to the i-clock 0 q-clock is phase-shifted less than 180 compared to the i-clock 6 clkqcalib 0 q-clock is automatically calibrated after the reset phase and after data reception from the card 1 no calibration is performed automatically 5 0 - this value must not be changed 4 to 0 clkqdelay[4:0] - this register shows the number of delay elements used to generate a 90 phase-shift of the i-clock to obtain the q-clock. it can be written directly by the microprocessor or by the automatic calibration cycle.
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 68 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.5 page 4: rf timing and channel redundancy 10.5.5.1 page register selects the page register; see section 10.5.1.1 p age register on page 50 . 10.5.5.2 rxwait register selects the time interval after transmission, before the receiver starts. 10.5.5.3 channelredundancy register selects kind and mode of checking the data integrity on the rf channel. table 99. rxwait register (address: 21h) reset value: 0000 0101b, 06h bit allocation bit 7 6 5 4 3 2 1 0 symbol rxwait[7:0] access r/w table 100. rxwait register bit descriptions bit symbol function 7 to 0 rxwait[7:0] after data transmission, the activation of the receiver is delayed for rxwait bit-clock cycles. during this frame guard time any signal on pin rx is ignored. table 101. channelredundancy register (address: 22h) reset value: 0000 0011b, 03h bit allocation bit 7 6 5 4 3 2 1 0 symbol 00 crc3309 crc8 rxcrcen txcrcen parityodd parityen access r/w r/w r/w r/w r/w r/w r/w r/w table 102. channelredundancy bit descriptions bit symbol value function 7 to 6 00 - this value must not be changed 5 crc3309 1 crc calculation is performed using iso/iec 3309 (iso/iec 14443 b) and iso/iec 15693 0 crc calculation is performed using iso/iec 14443 a and i-code1 4 crc8 1 an 8-bit crc is calculated 0 a 16-bit crc is calculated 3 rxcrcen 1 the last byte(s) of a received frame are interpreted as crc bytes. if the crc is correct, the crc bytes are not passed to the fifo. if the crc bytes are incorrect, the crcerr ?ag is set. 0 no crc is expected 2 txcrcen 1 a crc is calculated over the transmitted data and the crc bytes are appended to the data stream 0 no crc is transmitted
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 69 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) [1] when used with iso/iec 14443 a, this bit must be set to logic 1. 10.5.5.4 crcpresetlsb register lsb of the preset value for the crc register. [1] to use the iso/iec 15693 functionality, the crcpresetlsb register has to be set to ffh. 10.5.5.5 crcpresetmsb register msb of the preset value for the crc register. 10.5.5.6 timeslotperiod register de?nes the time-slot period for i-code1 protocol. 1 parityodd 1 odd parity is generated or expected [1] 0 even parity is generated or expected 0 parityen 1 a parity bit is inserted in the transmitted data stream after each byte and expected in the received data stream after each byte (mifare, iso/iec 14443 a) 0 no parity bit is inserted or expected (iso/iec 14443 b) table 102. channelredundancy bit descriptions continued bit symbol value function table 103. crcpresetlsb register (address: 23h) reset value: 0101 0011b, 63h bit allocation bit 7 6 5 4 3 2 1 0 symbol crcpresetlsb[7:0] access r/w table 104. crcpresetlsb register bit descriptions bit symbol description 7 to 0 crcpresetlsb[7:0] de?nes the start value for crc calculation. this value is loaded into the crc at the beginning of transmission, reception and the calccrc command (if crc calculation is enabled) [1] . table 105. crcpresetmsb register (address: 24h) reset value: 0101 0011b, 63h bit allocation bit 7 6 5 4 3 2 1 0 symbol crcpresetmsb[7:0] access r/w table 106. crcpresetmsb bit descriptions bit symbol description 7 to 0 crcpresetmsb[7:0] de?nes the starting value for crc calculation. this value is loaded into the crc at the beginning of transmission, reception and the calccrc command (if the crc calculation is enabled) remark: this register is not relevant if crc8 is set to logic 1. table 107. timeslotperiod register (address: 25h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol timeslotperiod[7:0] access r/w
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 70 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.5.7 mfoutselect register selects the internal signal applied to pin mfout. [1] only valid for mifare and iso/iec 14443 a communication at 106 kbd. 10.5.5.8 preset27 register table 108. timeslotperiod register bit descriptions bit symbol description 7 to 0 timeslotperiod[7:0] de?nes the time between automatically transmitted frames. to send a quit frame using the i-code1 protocol it is necessary to relate to the beginning of the command frame. the timeslotperiod starts at the end of the command transmission. see section 9.5.1.5 on page 26 for additional information. table 109. mfoutselect register (address: 26h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 000 timeslotperiodmsb 0 mfoutselect[2:0] access r/w r/w r/w r/w r/w r/w table 110. mfoutselect register bit descriptions bit symbol value description 7 to 5 000 - these values must not be changed 4 timeslotperiodmsb - msb of value timeslotperiod; see t ab le 107 on page 69 for more detailed information 3 0 - this value must not be changed 2 to 0 mfoutselect[2:0] de?nes which signal is routed to pin mfout: 000 constant low 001 constant high 010 modulation signal (envelope) from the internal encoder, (miller coded) 011 serial data stream, not miller encoded 100 output signal of the energy carrier demodulator (card modulation signal) [1] 101 output signal of the subcarrier demodulator (manchester encoded card signal) [1] 110 reserved 111 reserved table 111. preset27 (address: 27h) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol x x x x x x x x access w w w w w w w w
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 71 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.6 page 5: fifo, timer and irq pin con?guration 10.5.6.1 page register selects the page register; see section 10.5.1.1 p age register on page 50 . 10.5.6.2 fifolevel register de?nes the levels for fifo under?ow and over?ow warning. 10.5.6.3 timerclock register selects the divider for the timer clock. table 112. fifolevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation bit 7 6 5 4 3 2 1 0 symbol 00 waterlevel[5:0] access r/w r/w r/w table 113. fifolevel register bit descriptions bit symbol description 7 to 6 00 these values must not be changed 5 to 0 waterlevel[5:0] de?nes, the warning level of a fifo buffer over?ow or under?ow: hialert is set to logic 1 if the remaining fifo buffer space is equal to, or less than, waterlevel[5:0] bits in the fifo buffer. loalert is set to logic 1 if equal to, or less than, waterlevel[5:0] bits in the fifo buffer. table 114. timerclock register (address: 2ah) reset value: 0000 0111b, 07h bit allocation bit 7 6 5 4 3 2 1 0 symbol 00 tautorestart tprescaler[4:0] access rw rw rw rw table 115. timerclock register bit descriptions bit symbol value function 7 to 6 00 - these values must not be changed 5 tautorestart 1 the timer automatically restarts its countdown from the treloadvalue[7:0] instead of counting down to zero 0 the timer decrements to zero and register interruptirq timerirq bit is set to logic 1 4 to 0 tprescaler[4:0] - de?nes the timer clock frequency (f timerclock ). the tprescaler[4:0] can be adjusted from 0 to 21. the following formula is used to calculate the timerclock frequency (f timerclock ): f timerclock = 13.56 mhz / 2 tprescaler [mhz]
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 72 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.6.4 timercontrol register selects start and stop conditions for the timer. 10.5.6.5 timerreload register de?nes the preset value for the timer. table 116. timercontrol register (address: 2bh) reset value: 0000 0110b, 06h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0000 tstoprxend tstoprxbegin tstarttxend tstarttxbegin access r/w r/w r/w r/w r/w table 117. timercontrol register bit descriptions bit symbol value description 7 to 4 0000 - these values must not be changed 3 tstoprxend 1 the timer automatically stops when data reception ends 0 the timer is not in?uenced by this condition 2 tstoprxbegin 1 the timer automatically stops when the ?rst valid bit is received 0 the timer is not in?uenced by this condition 1 tstarttxend 1 the timer automatically starts when data transmission ends. if the timer is already running, the timer restarts by loading treloadvalue[7:0] into the timer. 0 the timer is not in?uenced by this condition 0 tstarttxbegin 1 the timer automatically starts when the ?rst bit is transmitted. if the timer is already running, the timer restarts by loading treloadvalue[7:0] into the timer. 0 the timer is not in?uenced by this condition table 118. timerreload register (address: 2ch) reset value: 0000 1010b, 0ah bit allocation bit 7 6 5 4 3 2 1 0 symbol treloadvalue[7:0] access r/w table 119. timerreload register bit descriptions bit symbol description 7 to 0 treloadvalue[7:0] on a start event, the timer loads the treloadvalue[7:0] value. changing this register only affects the timer on the next start event. if treloadvalue[7:0] is set to logic 0 the timer cannot start.
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 73 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.6.6 irqpincon?g register con?gures the output stage for pin irq. 10.5.6.7 preset2e register 10.5.6.8 preset2f register 10.5.7 page 6: reserved 10.5.7.1 page register selects the page register; see section 10.5.1.1 p age register on page 50 . 10.5.7.2 reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h remark: these registers are reserved for future use. table 120. irqpincon?g register (address: 2dh) reset value: 0000 0010b, 02h bit allocation bit 7 6 5 4 3 2 1 0 symbol 000000 irqinv irqpushpull access r/w r/w r/w table 121. irqpincon?g register bit descriptions bit symbol value description 7 to 2 000000 - these values must not be changed 1 irqinv 1 inverts the signal on pin irq with respect to bit irq 0 the signal on pin irq is not inverted and is the same as bit irq 0 irqpushpull 1 pin irq functions as a standard cmos output pad 0 pin irq functions as an open-drain output pad table 122. preset2e register (address: 2eh) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access wwwwwwww table 123. preset2f register (address: 2fh) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access wwwwwwww table 124. reserved registers (address: 31h, 32h, 33h, 34h, 35h, 36h, 37h) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access r/w r/w r/w r/w r/w r/w r/w r/w
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 74 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.8 page 7: test control 10.5.8.1 page register selects the page register; see section 10.5.1.1 p age register on page 50 . 10.5.8.2 reserved register 39h remark: this register is reserved for future use. 10.5.8.3 testanaselect register selects analog test signals. table 125. reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access wwwwwwww table 126. testanaselect register (address: 3ah) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0000 testanaoutsel[4:0] access w w table 127. testanaselect bit descriptions bit symbol value description 7 to 4 0000 - these values must not be changed 3 to 0 testanaoutsel[4:0] selects the internal analog signal to be routed to pin aux. see section 15.2.2 on page 112 for detailed information. the settings are as follows: 0 vmid 1 vbandgap 2 vrxfolli 3 vrxfollq 4 vrxampi 5 vrxampq 6 vcorrni 7 vcorrnq 8 vcorrdi 9 vcorrdq a vevall b vevalr c vtemp d reserved e reserved f reserved
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 75 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.8.4 reserved register 3bh remark: this register is reserved for future use. 10.5.8.5 reserved register 3ch remark: this register is reserved for future use. 10.5.8.6 testdigiselect register selects digital test mode. table 128. reserved register (address: 3bh) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access wwwwwwww table 129. reserved register (address: 3ch) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access wwwwwwww table 130. testdigiselect register (address: 3dh) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol signaltomfout testdigisignalsel[6:0] access w w table 131. testdigiselect register bit descriptions bit symbol value description 7 signaltomfout 1 overrules the mfoutselect[2:0] setting and routes the digital test signal de?ned with the testdigisignalsel[6:0] bits to pin mfout 0 mfoutselect[2:0] de?nes the signal on pin mfout 6 to 0 testdigisignalsel[6:0] - selects the digital test signal to be routed to pin mfout. refer to section 15.2.3 on page 113 for detailed information. the following lists the signal names for the testdigisignalsel[6:0] addresses: f4h s_data e4h s_valid d4h s_coll c4h s_clock b5h rd_sync a5h wr_sync 96h int_clock 83h bpsk_out e2h bpsk_sig
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 76 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 10.5.8.7 reserved registers 3eh, 3fh remark: this register is reserved for future use. 11. clrc632 command set clrc632 operation is determined by an internal state machine capable of performing a command set. the commands can be started by writing the command code to the command register. arguments and/or data necessary to process a command are mainly exchanged using the fifo buffer. ? each command needing a data stream (or data byte stream) as an input immediately processes the data in the fifo buffer ? each command that requires arguments only starts processing when it has received the correct number of arguments from the fifo buffer ? the fifo buffer is not automatically cleared at the start of a command. it is, therefore, possible to write command arguments and/or the data bytes into the fifo buffer before starting a command. ? each command (except the startup command) can be interrupted by the microprocessor writing a new command code to the command register e.g. the idle command. 11.1 clrc632 command overview table 132. reserved register (address: 3eh, 3fh) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access wwwwwwww table 133. clrc632 commands overview command value action fifo communication arguments and data sent data received startup 3fh runs the reset and initialization phase. see section 11.1.2 on page 78 . remark: this command can only be activated by power-on or hard resets. -- idle 00h no action; cancels execution of the current command. see section 11.1.3 on page 78 -- transmit 1ah transmits data from the fifo buffer to the card. see section 11.2.1 on page 79 data stream - receive 16h activates receiver circuitry. before the receiver starts, the state machine waits until the time de?ned in the rxwait register has elapsed. see section 11.2.2 on page 82 . remark: this command may be used for test purposes only, since there is no timing relationship to the transmit command. - data stream
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 77 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) [1] this command is the combination of the transmit and receive commands. [2] relates to mifare mini/mifare 1k/mifare 4k security. transceive [1] 1eh transmits data from fifo buffer to the card and automatically activates the receiver after transmission. the receiver waits until the time de?ned in the rxwait register has elapsed before starting. see section 11.2.3 on page 85 . data stream data stream writee2 01h reads data from the fifo buffer and writes it to the eeprom. see section 11.4.1 on page 93 . start address lsb - start address msb data byte stream reade2 03h reads data from the eeprom and sends it to the fifo buffer. see section 11.4.2 on page 95 . remark: keys cannot be read back start address lsb data bytes start address msb number of data bytes loadkeye2 0bh copies a key from the eeprom into the key buffer [2] see section 11.7.1 on page 97 . start address lsb - start address msb loadkey 19h reads a key from the fifo buffer and loads it into the key buffer [2] . see section 11.7.2 on page 97 . remark: the key has to be prepared in a speci?c format (refer to section 9.2.3.1 k e y f or mat on page 18 ) byte 0 lsb - byte 1 byte 10 byte 11 msb authent1 0ch performs the ?rst part of card authentication using the crypto1 algorithm [2] . see section 11.7.3 on page 98 . card authent1 command - card block address card serial number lsb card serial number byte 1 card serial number byte 2 card serial number msb authent2 14h performs the second part of card authentication using the crypto1 algorithm [2] . see section 11.7.4 on page 98 . -- loadcon?g 07h reads data from eeprom and initializes the clrc632 registers. see section 11.5.1 on page 95 . start address lsb - start address msb calccrc 12h activates the crc coprocessor remark: the result of the crc calculation is read from the crcresultlsb and crcresultmsb registers. see section 11.5.2 on page 96 . data byte stream - table 133. clrc632 commands overview continued command value action fifo communication arguments and data sent data received
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 78 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.1.1 basic states 11.1.2 startup command 3fh remark: this command can only be activated by a power-on or hard reset. the startup command runs the reset and initialization phases. it does not need or return, any data. it cannot be activated by the microprocessor but is automatically started after one of the following events: ? power-on reset (por) caused by power-up on pin dvdd ? por caused by power-up on pin avdd ? negative edge on pin rstpd the reset phase comprises an asynchronous reset and con?guration of certain register bits. the initialization phase con?gures several registers with values stored in the eeprom. when the startup command ?nishes, the idle command is automatically executed. remark: ? the microprocessor must not write to the clrc632 while it is still executing the startup command. to avoid this, the microprocessor polls for the idle command to determine when the initialization phase has ?nished; see section 9.7.4 on page 30 . ? when the startup command is active, it is only possible to read from the page 0 register. ? the startup command cannot be interrupted by the microprocessor. 11.1.3 idle command 00h the idle command switches the clrc632 to its inactive state where it waits for the next command. it does not need or return, any data. the device automatically enters the idle state when a command ?nishes. when this happens, the clrc632 sends an interrupt request by setting bit idleirq. when triggered by the microprocessor, the idle command can be used to stop execution of all other commands (except the startup command) but this does not generate an interrupt request (idleirq). remark: stopping command execution with the idle command does not clear the fifo buffer. table 134. startup command 3fh command value action arguments and data returned data startup 3fh runs the reset and initialization phase - - table 135. idle command 00h command value action arguments and data returned data idle 00h no action; cancels current command execution --
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 79 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.2 commands for iso/iec 14443 a card communication the clrc632 is a fully iso/iec 14443 a, iso/iec 14443 b, iso/iec 15693 and i-code1 compliant reader ic. this enables the command set to be more ?exible and generalized when compared to dedicated mifare or i-code1 reader ics. section 11.2.1 to section 11.2.5 describe the command set for iso/iec 14443 a card communication and related communication protocols. 11.2.1 transmit command 1ah the transmit command reads data from the fifo buffer and sends it to the transmitter. it does not return any data. the transmit command can only be started by the microprocessor. 11.2.1.1 using the transmit command to transmit data, one of the following sequences can be used: 1. all data to be transmitted to the card is written to the fifo buffer while the idle command is active. then the command code for the transmit command is written to the command register. remark: this is possible for transmission of a data stream up to 64 bytes. 2. the command code for the transmit command is stored in the command register. since there is not any data available in the fifo buffer, the command is only enabled but transmission is not activated. data transmission starts when the ?rst data byte is written to the fifo buffer. to generate a continuous data stream on the rf interface, the microprocessor must write the subsequent data bytes into the fifo buffer in time. remark: this allows transmission of any data stream length but it requires data to be written to the fifo buffer in time. 3. part of the data transmitted to the card is written to the fifo buffer while the idle command is active. then the command code for the transmit command is written to the command register. while the transmit command is active, the microprocessor can send further data to the fifo buffer. this is then appended by the transmitter to the transmitted data stream. remark: this allows transmission of any data stream length but it requires data to be written to the fifo buffer in time. when the transmitter requests the next data byte to ensure the data stream on the rf interface is continuous and the fifo buffer is empty, the transmit command automatically terminates. this causes the internal state machine to change its state from transmit to idle. when the data transmission to the card is ?nished, the txirq ?ag is set by the clrc632 to indicate to the microprocessor transmission is complete. remark: if the microprocessor overwrites the transmit code in the command register with another command, transmission stops immediately on the next clock cycle. this can produce output signals that are not in accordance with iso/iec 14443 a. table 136. transmit command 1ah command value action arguments and data returned data transmit 1ah transmits data from fifo buffer to card data stream -
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 80 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.2.1.2 rf channel redundancy and framing each iso/iec 14443 a transmitted frame consists of a start of frame (sof) pattern, followed by the data stream and is closed by an end of frame (eof) pattern. these different phases of the transmission sequence can be monitored using the primarystatus register modemstate[2:0] bit; see section 11.2.4 on page 85 . depending on the setting of the channelredundancy register bit txcrcen, the crc is calculated and appended to the data stream. the crc is calculated according to the settings in the channelredundancy register. parity generation is handled according to the channelredundancy register parityen and parityodd bits settings. 11.2.1.3 transmission of bit oriented frames the transmitter can be con?gured to send an incomplete last byte. to achieve this the bitframing registers txlastbits[2:0] bits must be set at above zero (for example, 1). this is shown in figure 16 . figure 16 shows the data stream if bit parityen is set in the channelredundancy register. all fully transmitted bytes are followed by a parity check bit but the incomplete byte is not followed by a parity check bit. after transmission, the txlastbits[2:0] bits are automatically cleared. remark: if the txlastbits[2:0] bits are not equal to zero, crc generation must be disabled. this is done by clearing the channelredundancy register txcrcen bit. 11.2.1.4 transmission of frames with more than 64 bytes to generate frames of more than 64 bytes, the microprocessor must write data to the fifo buffer while the transmit command is active. the state machine checks the fifo buffer status when it starts transmitting the last bit of the data stream; the check time is marked in figure 17 with arrows. fig 16. transmitting bit oriented frames 001aak618 txlastbits = 0 txlastbits = 7 txlastbits = 1 0 7 p 0 7 p sof sof sof eof eof eof 0 7 p 0 6 0 7 p 0
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 81 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) as long as the internal accept further data signal is logic 1, further data can be written to the fifo buffer. the clrc632 appends this data to the data stream transmitted using the rf interface. if the internal accept further data signal is logic 0, the transmission terminates. all data written to the fifo buffer after accept further data signal was set to logic 0 is not transmitted, however, it remains in the fifo buffer. remark: if parity generation is enabled (parityen = logic 1), the parity bit is the last bit transmitted. this delays the accept further data signal by a duration of one bit. if the txlastbits[2:0] bits are not zero, the last byte is not transmitted completely. only the number of bits set by txlastbits[2:0], starting with the least signi?cant bit are transmitted. this means that the internal state machine has to check the fifo buffer status at an earlier point in time; see figure 18 . since in this example txlastbits[2:0] = 4, transmission stops after bit 3 is transmitted and the frame is completed with an eof, if con?gured. fig 17. timing for transmitting byte oriented frames fig 18. timing for transmitting bit oriented frames 001aak619 accept further data check fifo empty txdata fifo empty fifolength[6:0] 0x01 0x00 txlastbits[2:0] txlastbits = 0 7 0 7 70 001aak620 accept further data check fifo empty txdata fifo empty fifolength[6:0] 0x01 0x00 0x01 0x00 txlastbits[2:0] txlastbits = 4 nwr (fifo data) 7 0 3 4 7 0 3 4
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 82 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) figure 18 also shows write access to the fifodata register just before the fifo buffers status is checked. this leads to fifo empty state being held low which keeps the accept further data active. the new byte written to the fifo buffer is transmitted using the rf interface. accept further data is only changed by the check fifo empty function. this function veri?es fifo empty for one bit duration before the last expected bit transmission. 11.2.2 receive command 16h the receive command activates the receiver circuitry. all data received from the rf interface is written to the fifo buffer. the receive command can be started either using the microprocessor or automatically during execution of the transceive command. remark: this command can only be used for test purposes since there is no timing relationship to the transmit command. 11.2.2.1 using the receive command after starting the receive command, the internal state machine decrements to the rxwait register value on every bit-clock. the analog receiver circuitry is prepared and activated from 3 down to 1. when the counter reaches 0, the receiver starts monitoring the incoming signal at the rf interface. when the signal strength reaches a level higher than the rxthreshold register minlevel[3:0] bits value, it starts decoding. the decoder stops when the signal can longer be detected on the receiver input pin rx. the decoder sets bit rxirq indicating receive termination. the different phases of the receive sequence are monitored using the primarystatus register modemstate[2:0] bits; see section 11.2.4 on page 85 . remark: since the counter values from 3 to 0 are needed to initialize the analog receiver circuitry, the minimum value for rxwait[7:0] is 3. 11.2.2.2 rf channel redundancy and framing the decoder expects the sof pattern at the beginning of each data stream. when the sof is detected, it activates the serial-to-parallel converter and gathers the incoming data bits. every completed byte is forwarded to the fifo buffer. table 137. transmission of frames of more than 64 bytes frame de?nition veri?cation at: 8-bit with parity 8 th bit 8-bit without parity 7 th bit x-bit without parity (x - 1) th bit table 138. receive command 16h command value action arguments and data returned data receive 16h activates receiver circuitry - data stream
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 83 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) if an eof pattern is detected or the signal strength falls below the rxthreshold register minlevel[3:0] bits setting, both the receiver and the decoder stop. then the idle command is entered and an appropriate response for the microprocessor is generated (interrupt request activated, status ?ags set). when the channelredundancy register bit rxcrcen is set, a crc block is expected. the crc block can be one byte or two bytes depending on the channelredundancy register crc8 bit setting. remark: if the crc block received is correct, it is not sent to the fifo buffer. this is realized by shifting the incoming data bytes through an internal buffer of either one or two bytes (depending on the de?ned crc). the crc block remains in this internal buffer. consequently, all data bytes in the fifo buffer are delayed by one or two bytes. if the crc fails, all received bytes are sent to the fifo buffer including the faulty crc. if parityen is set in the channelredundancy register, a parity bit is expected after each byte. if parityodd = logic 1, the expected parity is odd, otherwise even parity is expected. 11.2.2.3 collision detection if more than one card is within the rf ?eld during the card selection phase, they both respond simultaneously. the clrc632 supports the algorithm de?ned in iso/iec 14443 a to resolve card serial number data collisions by performing the anti-collision procedure. the basis for this procedure is the ability to detect bit-collisions. bit-collision detection is supported by the manchester coding bit encoding scheme used in the clrc632. if in the ?rst and second half-bit of a subcarrier, modulation is detected, instead of forwarding a 1-bit or 0-bit, a bit-collision is indicated. the clrc632 uses the rxthreshold register colllevel[3:0] bits setting to distinguish between a 1-bit or 0-bit and a bit-collision. if the amplitude of the half-bit with smaller amplitude is larger than that de?ned by the colllevel[3:0] bits, the clrc632 ?ags a bit-collision using the error ?ag collerr. if a bit-collision is detected in a parity bit, the parityerr ?ag is set. on a detected collision, the receiver continues receiving the incoming data stream. in the case of a bit-collision, the decoder sends logic 1 at the collision position. remark: as an exception, if bit zeroaftercoll is set, all bits received after the ?rst bit-collision are forced to zero, regardless whether a bit-collision or an unequivocal state has been detected. this feature makes it easier for the control software to perform the anti-collision procedure as de?ned in iso/iec 14443 a. when the ?rst bit collision in a frame is detected, the bit-collision position is stored in the collpos register. t ab le 139 shows the collision positions.
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 84 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) parity bits are not counted in the collpos register because bit-collisions in parity bit occur after bit-collisions in the data bits. if a collision is detected in the sof, a frame error is ?agged and no data is sent to the fifo buffer. in this case, the receiver continues to monitor the incoming signal. it generates the correct noti?cations to the microprocessor when the end of the faulty input stream is detected. this helps the microprocessor to determine when it is next allowed to send data to the card. 11.2.2.4 receiving bit oriented frames the receiver can manage byte streams with incomplete bytes which result in bit-oriented frames. to support this, the following values may be used: ? bitframing registers rxalign[2:0] bits select a bit offset for the ?rst incoming byte. for example, if rxalign[2:0] = 3, the ?rst 5 bits received are forwarded to the fifo buffer. further bits are packed into bytes and forwarded. after reception, rxalign[2:0] is automatically cleared. if rxalign[2:0] = logic 0, all incoming bits are packed into one byte. ? rxlastbits[2:0] returns the number of bits valid in the last received byte. for example, if rxlastbits[2:0] evaluates to 5 bits at the end of the received command, the 5 least signi?cant bits are valid. if the last byte is complete, rxlastbits[2:0] evaluates to zero. rxlastbits[2:0] is only valid if a frame error is not indicated by the framingerr ?ag. if rxalign[2:0] is not zero and parityen is active, the ?rst parity bit is ignored and not checked. 11.2.2.5 communication errors the events which can set error ?ags are shown in t ab le 140 . table 139. return values for bit-collision positions collision in bit collpos register value (decimal) sof 0 least signi?cant bit (lsb) of the least signi?cant byte (lsbyte) 1 most signi?cant bit (msb) of the lsbyte 8 lsb of second byte 9 msb of second byte 16 lsb of third byte 17 table 140. communication error table cause flag bit received data did not start with the sof pattern framingerr crc block is not equal to the expected value crcerr received data is shorter than the crc block crcerr the parity bit is not equal to the expected value (i.e. a bit-collision, not parity) parityerr a bit-collision is detected collerr
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 85 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.2.3 transceive command 1eh the transceive command ?rst executes the transmit command (see section 11.2.1 on page 79 ) and then starts the receive command (see section 11.2.2 on page 82 ). all data transmitted is sent using the fifo buffer and all data received is written to the fifo buffer. the transceive command can only be started by the microprocessor. remark: to adjust the timing relationship between transmitting and receiving, use the rxwait register. this register is used to de?ne the time delay between the last bit transmitted and activation of the receiver. in addition, the bitphase register determines the phase-shift between the transmitter and receiver clock. 11.2.4 states of the card communication the status of the transmitter and receiver state machine can be read from bits modemstate[2:0] in the primarystatus register. the assignment of modemstate[2:0] to the internal action is shown in t ab le 142 . table 141. transceive command 1eh command value action arguments and data returned data transceive 1eh transmits data from fifo buffer to the card and then automatically activates the receiver data stream data stream table 142. meaning of modemstate modemstate [2:0] state description 000 idle transmitter and/or receiver are not operating 001 txsof transmitting the sof pattern 010 txdata transmitting data from the fifo buffer (or redundancy crc check bits) 011 txeof transmitting the eof pattern 100 gotorx1 intermediate state passed, when receiver starts gotorx2 intermediate state passed, when receiver ?nishes 101 preparerx waiting until the rxwait register time period expires 110 awaitingrx receiver activated; waiting for an input signal on pin rx
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 86 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.2.5 card communication state diagram fig 19. card communication state diagram 001aak621 end of receive frame and rxmultiple = 0 rxmultiple = 1 eof transmitted and command = transceive fifo not empty and command = transmit or transceive command = receive command = transmit, receive or transceive set command register = idle (000) awaiting rx (110) receiving (111) gotorx2 (100) prepare rx (101) gotorx1 (100) txeof (011) txdata (010) txsof (001) idle (000) sof transmitted next bit clock data transmitted rxwaitc[7:0] = 0 eof transmitted and command = transmit signal strength > minlevel[3:0] frame received
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 87 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.3 i-code1 and iso/iec 15693 label communication commands the clrc632 is a fully iso/iec 14443 a, iso/iec 14443 b, iso/iec 15693 and i-code1 compliant reader ic. this enables the command set to be more ?exible and generalized when compared to dedicated mifare or i-code1 reader ics. section 11.3.1 to section 11.3.5 give an overview of the command set for i-code1 and iso/iec 15693 card communication and related communication protocols. 11.3.1 transmit command 1ah the transmit command reads data from the fifo buffer and sends it to the transmitter. it does not return any data. the transmit command can only be started by the microprocessor. 11.3.1.1 using the transmit command to transmit data, one of the following sequences can be used: 1. all data to be transmitted to the label is written to the fifo buffer while the idle command is active. then the command code for the transmit command is written to the command register. remark: this is possible for transmission of a data stream up to 64 bytes long. 2. the command code for the transmit command is stored in the command register. since there is not any data available in the fifo buffer, the command is only enabled but transmission is not triggered. data transmission starts when the ?rst data byte is written to the fifo buffer. to generate a continuous data stream on the rf interface, the microprocessor must write the subsequent data bytes into the fifo buffer in time. remark: this allows transmission of any data stream length but it requires data to be written to the fifo buffer in time. 3. part of the data transmitted to the label is written to the fifo buffer while the idle command is active. then the command code for the transmit command is written to the command register. while the transmit command is active, the microprocessor can send further data to the fifo buffer. this is then appended by the transmitter to the transmitted data stream. remark: this allows transmission of any data stream length but it requires data to be written to the fifo buffer in time. when the transmitter requests the next data byte, to ensure that the data stream on the rf interface is continuous and the fifo buffer is empty, the transmit command automatically terminates. this causes the internal state machine to change its state from transmit to idle. when the data transmission to the label is ?nished, the txirq ?ag is set by the clrc632 to indicate transmission is complete to the microprocessor. remark: if the microprocessor overwrites the transmit code in the command register with another command, transmission stops immediately on the next clock cycle. this can produce output signals that do not comply with the iso/iec 15693 standard or the i-code1 protocol. table 143. transmit command 1ah command value action arguments and data returned data transmit 1ah transmits data from fifo buffer to the label data stream -
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 88 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.3.1.2 rf channel redundancy and framing each transmitted iso/iec 15693 frame consists of a start of frame (sof) pattern, followed by the data stream and is closed by an end of frame (eof) pattern. all i-code1 command frames consists of a start pulse followed by the data stream. the i-code1 commands have a ?xed length and do not need an eof. the phases of the transmission sequence are monitored using the primarystatus registers modemstate[2:0] bits; see section 11.2.4 on page 85 . depending on the channelredundancy register txcrcen bit setting, the crc is calculated and appended to the data stream. the crc is calculated using the channelredundancy register settings. 11.3.1.3 transmission of frames of more than 64 bytes to generate frames of more than 64 bytes of data, the microprocessor has to write data to the fifo buffer while the transmit command is active. the state machine checks the fifo buffer status when it starts transmitting the last bit of the data stream (the check time is shown in figure 20 with arrows). as long as the internal accept further data signal is logic 1 further data can be written to the fifo buffer. the clrc632 appends this data to the data stream transmitted using the rf interface. if the internal accept further data signal is logic 0 the transmission terminates. all data written to the fifo buffer after accept further data signal was set to logic 0 is not transmitted, however, it remains in the fifo buffer. 11.3.2 receive command 16h the receive command activates the receiver circuitry. all data received from the rf interface is written to the fifo buffer. the receive command can be started either by the microprocessor or automatically during execution of the transceive command. fig 20. timing for transmitting byte oriented frames 001aak619 accept further data check fifo empty txdata fifo empty fifolength[6:0] 0x01 0x00 txlastbits[2:0] txlastbits = 0 7 0 7 70 table 144. receive command 16h command value action arguments and data returned data receive 16h activates receiver circuitry - data stream
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 89 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) remark: this command may be used for test purposes only, since there is no timing relation to the transmit command. 11.3.2.1 using the receive command after starting the receive command the internal state machine decrements the rxwait register value on every bit-clock. the analog receiver circuitry is prepared and activated from 3 down to 1. when the counter reaches 0, the receiver starts monitoring the incoming signal using the rf interface. if the signal strength reaches a level above the value set in the rxthreshold registers minlevel[3:0] bits, the receiver starts decoding. the decoder stops when the signal cannot be detected on the receiver input pin rx. the decoder sets the rxirq ?ag bit to indicate that the operation has ?nished. the receive sequence phases can be monitored using bits modemstatus[2:0] in the primarystatus register; see section 11.2.4 on page 85 . remark: the minimum value for rxwait[7:0] is 3 because counter values from 3 to 0 are needed to initialize the analog receiver circuitry. 11.3.2.2 rf channel redundancy and framing in iso/iec 15693 mode, the decoder expects a sof pattern at the beginning of each data stream. when a sof is detected, it activates the serial-to-parallel converter and gathers the incoming data bits. if an eof pattern (iso/iec 15693) is detected or the signal strength falls below the minlevel value, the receiver and the decoder stop, the idle command is entered and an appropriate response for the microprocessor is generated (interrupt request activated, status ?ags set). in i-code1 mode, the decoder does not expect a sof pattern at the beginning of each data stream. it activates the serial-to-parallel converter on the ?rst received bit of the data. every full byte is then sent to the fifo buffer. if channelredundancy register bit rxcrcen is set a crc block is expected. the crc block may be one byte or two bytes based on the channelredundancy registers crc8 bit. remark: if it is correct, the crc block is not forwarded to the fifo buffer. the crc is realized by shifting the incoming data bytes through an internal buffer of one or two bytes (depending on the de?ned crc). the crc block remains in this internal buffer. consequently, all data bytes in the fifo buffer are delayed by one or two bytes. if the crc fails, all bytes received are forwarded to the fifo buffer (including the faulty crc). 11.3.2.3 collision detection if more than one label is within the rf ?eld during the label selection phase, they will respond simultaneously. the clrc632 supports the algorithm de?ned in iso/iec 15693 as well as the i-code1 anti-collision algorithm to resolve label serial number data collisions using the anti-collision procedure. the basis for this procedure is the ability to detect bit-collisions. bit-collision detection is supported by the manchester coding bit encoding scheme used. if in the ?rst and second half-bit of a bit a subcarrier modulation is detected, instead of forwarding a 1-bit or a 0-bit, a bit-collision is ?agged.
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 90 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) to distinguish between a 1-bit or 0-bit from a bit-collision, the rxthreshold registers colllevel[3:0] value is used. if the amplitude of the half-bit with smaller amplitude is larger than de?ned by colllevel[3:0], a bit-collision is ?agged by setting the collerr error ?ag. the receiver continues receiving the incoming data stream independently from the detected collision. in case of a bit-collision, the decoder forwards logic 1 at the collision position. remark: as an exception, if bit zeroaftercoll is set, all bits received after the ?rst bit-collision are forced to zero, regardless of whether a bit-collision or an unequivocal state has been detected. this feature makes it easier for the software to carry out the anti-collision procedure as de?ned in iso/iec 15693. when the ?rst bit-collision in a frame is detected, the bit position of the collision is stored in the collpos register. the collision positions are shown in t ab le 145 . if a collision is detected in the sof, a frame error is reported and no data is sent to the fifo buffer. in this case the receiver continues to monitor the incoming signal and generates the correct noti?cations to the microprocessor when the end of the faulty input stream is detected. this helps the microprocessor to determine the time when it is next allowed to send data to the label. 11.3.2.4 communication errors t ab le 146 shows the events that set error ?ags. table 145. return values for bit-collision positions collision in bit collpos register value (decimal) sof 0 least signi?cant bit (lsb) of the least signi?cant byte (lsbyte) 1 most signi?cant bit (msb) of the lsbyte 8 lsb of second byte 9 msb of second byte 16 lsb of third byte 17 table 146. communication error table cause bit set received data did not start with a sof pattern framingerr crc block is not equal to the expected value crcerr received data is shorter than the crc block crcerr a collision is detected collerr
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 91 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.3.3 transceive command 1eh the transceive command ?rst executes the transmit command (see section 11.2.1 on page 79 ) and then starts the receive command (see section 11.2.2 on page 82 ). all data to be transmitted is sent using the fifo buffer and all received data is written to the fifo buffer. the transceive command can be started only by the microprocessor. remark: to adjust the timing relationship between transmitting and receiving, use the rxwait register. this enables the time delay from the last bit transmitted until the receiver is activated to be de?ned. the bitphase register is used to set-up the phase-shift between the transmitter and the receiver clock. 11.3.4 label communication states the status of the transmitter and receiver state machine can be read from the primarystatus register modemstate[2:0] bits. the assignment of modemstate[2:0] to the internal action is shown in t ab le 148 . table 147. transceive command 1eh command value action arguments and data returned data transceive 1eh transmits data from fifo buffer to the label and then activates the receiver data stream data stream table 148. modemstate values modemstate [2:0] name description 000 idle transmitter and/or receiver are not operating 001 txsof transmitting the start of frame pattern 010 txdata transmitting data from the fifo buffer (or crc check bits) 011 txeof transmitting the end of frame pattern 100 gotorx1 intermediate state passed, when receiver starts gotorx2 intermediate state passed, when receiver ?nishes 101 preparerx waiting until the rxwait register wait time has elapsed 110 awaitingrx receiver activated; awaiting an input signal on pin rx 111 receiving receiving data
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 92 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.3.5 label communication state diagram (1) i-code1 does not have a sof and an eof. fig 21. label communication state diagram 001aak622 end of receive frame and rxmultiple = 0 time slot period = 0 rxmultiple = 1 time slot period > 0 time slot trigger and data fifo preparing to send the quit value eof transmitted and command = transceive fifo not empty and command = transmit or transceive command = receive command = transmit, receive or transceive set command register = idle (000) awaiting rx (110) receiving (111) gotorx2 (100) prepare rx (101) gotorx1 (100) txeof (011) txdata (010) txsof (001) idle (000) idle (000) sof transmitted next bit clock data transmitted rxwaitc[7:0] = 0 eof transmitted and command = transmit signal strength > minlevel[3:0] frame received rxmultiple = 0 time slot period > 0 time slot trigger and fifo data
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 93 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.4 eeprom commands 11.4.1 writee2 command 01h the writee2 command interprets the ?rst two bytes in the fifo buffer as the eeprom start byte address. any further bytes are interpreted as data bytes and are programmed into the eeprom, starting from the given eeprom start byte address. this command does not return any data. the writee2 command can only be started by the microprocessor. it will not stop automatically but has to be stopped explicitly by the microprocessor by issuing the idle command. 11.4.1.1 programming process one byte up to 16-byte can be programmed into the eeprom during a single programming cycle. the time needed is approximately 5.8 ms. the state machine copies all the prepared data bytes to the fifo buffer and then to the eeprom input buffer. the internal eeprom input buffer is 16 bytes long which is equal to the block size of the eeprom. a programming cycle is started if the last position of the eeprom input buffer is written or if the last byte of the fifo buffer has been read. the e2ready ?ag remains logic 0 when there are unprocessed bytes in the fifo buffer or the eeprom programming cycle is still in progress. when all the data from the fifo buffer are programmed into the eeprom, the e2ready ?ag is set to logic 1. together with the rising edge of e2ready the txirq interrupt request ?ag shows logic 1. this can be used to generate an interrupt when programming of all data is ?nished. remark: during the e2prom programming indicated by e2ready = logic 0, the writee2 command cannot be stopped using any other command. once e2ready = logic 1, the writee2 command can be stopped by the microprocessor by sending the idle command. table 149. writee2 command 01h command value action fifo arguments and data returned data writee2 01h get data from fifo buffer and write it to the eeprom start address lsb - start address msb - data byte stream -
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 94 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.4.1.2 timing diagram figure 22 shows programming ?ve bytes into the eeprom. assuming that the clrc632 ?nds and reads byte 0 before the microprocessor is able to write byte 1 (t prog,del = 300 ns). this causes the clrc632 to start the programming cycle (t prog ), which takes approximately 5.8 ms to complete. in the meantime, the microprocessor stores byte 1 to byte 4 in the fifo buffer. if the eeprom start byte address is 16ch then byte 0 is stored at that address. the clrc632 copies the subsequent data bytes into the eeprom input buffer. whilst copying byte 3, it detects that this data byte has to be programmed at the eeprom byte address 16fh. as this is the end of the memory block, the clrc632 automatically starts a programming cycle. next, byte 4 is programmed at the eeprom byte address 170h. as this is the last data byte, the e2ready and txirq ?ags are set indicating the end of the eeprom programming activity. although all data has been programmed into the e2prom, the clrc632 stays in the writee2 command. writing more data to the fifo buffer would lead to another eeprom programming cycle continuing from eeprom byte address 171h. the command is stopped using the idle command. 11.4.1.3 writee2 command error ?ags programming is restricted for eeprom block 0 (eeprom byte address 00h to 0fh). if you program these addresses, the accesserr ?ag is set and a programming cycle is not started. addresses above 1ffh are taken modulo 200h; see section 9.2 on page 12 for the eeprom memory organization. fig 22. eeprom programming timing diagram 001aak623 nwr data writee2 command active eeprom programming e2ready txirq write e2 addr lsb addr msb byte 0 byte 1 t prog,del byte 2 byte 3 byte 4 programming byte 0 t prog programming byte 1, byte 2 and byte 3 t prog programming byte 4 t prog idle command
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 95 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.4.2 reade2 command 03h the reade2 command interprets the ?rst two bytes stored in the fifo buffer as the eeprom starting byte address. the next byte speci?es the number of data bytes returned. when all three argument bytes are available in the fifo buffer, the speci?ed number of data bytes is copied from the eeprom into the fifo buffer, starting from the given eeprom starting byte address. the reade2 command can only be triggered by the microprocessor and it automatically stops when all data has been copied. 11.4.2.1 reade2 command error ?ags reading is restricted to eeprom blocks 8h to 1fh (key memory area). reading from these addresses sets the ?ag accesserr = logic 1. addresses above 1ffh are taken as modulo 200h; see section 9.2 on page 12 for the eeprom memory organization. 11.5 diverse commands 11.5.1 loadcon?g command 07h the loadcon?g command interprets the ?rst two bytes found in the fifo buffer as the eeprom starting byte address. when the two argument bytes are available in the fifo buffer, 32 bytes from the eeprom are copied into the control and other relevant registers, starting at the eeprom starting byte address. the loadcon?g command can only be started by the microprocessor and it automatically stops when all relevant registers have been copied. 11.5.1.1 register assignment the 32 bytes of eeprom content are written to the clrc632 registers 10h to register 2fh; see section 9.2 on page 12 for the eeprom memory organization. remark: the procedure for the register assignment is the same as it is for the startup initialization (see section 9.7.3 on page 30 ). the difference is, the eeprom starting byte address for the startup initialization is ?xed to 10h (block 1, byte 0). however, it can be chosen with the loadcon?g command. table 150. reade2 command 03h command value action arguments returned data reade2 03h reads eeprom data and stores it in the fifo buffer start address lsb data bytes start address msb number of data bytes table 151. loadcon?g command 07h command value action arguments and data returned data loadcon?g 07h reads data from eeprom and initializes the registers start address lsb - start address msb -
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 96 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.5.1.2 relevant loadcon?g command error ?ags valid eeprom starting byte addresses are between 10h and 60h. copying from block 8h to 1fh (keys) is restricted. reading from these addresses sets the ?ag accesserr = logic 1. addresses above 1ffh are taken as modulo 200h; see section 9.2 on page 12 for the eeprom memory organization. 11.5.2 calccrc command 12h the calccrc command takes all the data from the fifo buffer as the input bytes for the crc coprocessor. all data stored in the fifo buffer before the command is started is processed. this command does not return any data to the fifo buffer but the content of the crc can be read using the crcresultlsb and crcresultmsb registers. the calccrc command can only be started by the microprocessor and it does not automatically stop. it must be stopped by the microprocessor sending the idle command. if the fifo buffer is empty, the calccrc command waits for further input before proceeding. 11.5.2.1 crc coprocessor settings t ab le 153 shows the parameters that can be con?gured for the crc coprocessor. the crc polynomial for the 8-bit crc is ?xed to x 8 + x 4 + x 3 + x 2 + 1. the crc polynomial for the 16-bit crc is ?xed to x 16 + x 12 + x 5 + 1. 11.5.2.2 crc coprocessor status ?ags the crcready status ?ag indicates that the crc coprocessor has ?nished processing all the data bytes in the fifo buffer. when the crcready ?ag is set to logic 1, an interrupt is requested which sets the txirq ?ag. this supports interrupt driven use of the crc coprocessor. when crcready and txirq ?ags are set to logic 1 the content of the crcresultlsb and crcresultmsb registers and the crcerr ?ag are valid. the crcresultlsb and crcresultmsb registers hold the content of the crc, the crcerr ?ag indicates crc validity for the processed data. table 152. calccrc command 12h command value action arguments and data returned data calccrc 12h activates the crc coprocessor data byte stream - table 153. crc coprocessor parameters parameter value bit register crc register length 8-bit or 16-bit crc crc8 channelredundancy crc algorithm iso/iec 14443 a or iso/iec 3309 crc3309 channelredundancy crc preset value any crcpresetlsb crcpresetlsb crcpresetmsb crcpresetmsb
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 97 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.6 error handling during command execution if an error is detected during command execution, the primarystatus register err ?ag is set. the microprocessor can evaluate the status ?ags in the errorflag register to get information about the cause of the error. 11.7 mifare security commands 11.7.1 loadkeye2 command 0bh the loadkeye2 command interprets the ?rst two bytes found in the fifo buffer as the eeprom starting byte address. the eeprom bytes starting from the given starting byte address are interpreted as the key when stored in the correct key format as described in section 9.2.3.1 k e y f or mat on page 18 . when both argument bytes are available in the fifo buffer, the command executes. the loadkeye2 command can only be started by the microprocessor and it automatically stops after copying the key from the eeprom to the key buffer. 11.7.1.1 relevant loadkeye2 command error ?ags if the key format is incorrect (see section 9.2.3.1 k e y f or mat on page 18 ) an unde?ned value is copied into the key buffer and the keyerr ?ag is set. 11.7.2 loadkey command 19h table 154. errorflag register error ?ags overview error ?ag related commands keyerr loadkeye2, loadkey accesserr writee2, reade2, loadcon?g fifoovlf no speci?c commands crcerr receive, transceive, calccrc framingerr receive, transceive parityerr receive, transceive collerr receive, transceive table 155. loadkeye2 command 0bh command value action arguments and data returned data loadkeye2 0bh reads a key from the eeprom and puts it into the internal key buffer start address lsb - start address msb - table 156. loadkey command 19h command value action arguments and data returned data loadkey 19h reads a key from the fifo buffer and puts it into the key buffer byte 0 (lsb) - byte 1 - - byte 10 - byte 11 (msb) -
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 98 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) the loadkey command interprets the ?rst twelve bytes it ?nds in the fifo buffer as the key when stored in the correct key format as described in section 9.2.3.1 k e y f or mat on page 18 . when the twelve argument bytes are available in the fifo buffer they are checked and, if valid, are copied into the key buffer. the loadkey command can only be started by the microprocessor and it automatically stops after copying the key from the fifo buffer to the key buffer. 11.7.2.1 relevant loadkey command error ?ags all bytes requested are copied from the fifo buffer to the key buffer. if the key format is not correct (see section 9.2.3.1 k e y f or mat on page 18 ) an unde?ned value is copied into the key buffer and the keyerr ?ag is set. 11.7.3 authent1 command 0ch the authent1 command is a special transceive command; it sends six argument bytes to the card. the cards response is not sent to the microprocessor, it is used instead to authenticate the card to the clrc632 and vice versa. the authent1 command can be triggered only by the microprocessor. the sequence of states for this command are the same as those for the transceive command; see section 11.2.3 on page 85 . 11.7.4 authent2 command 14h the authent2 command is a special transceive command. it does not need any argument byte, however all the data needed to be sent to the card is assembled by the clrc632. the card response is not sent to the microprocessor but is used to authenticate the card to the clrc632 and vice versa. the authent2 command can only be started by the microprocessor. the sequence of states for this command are the same as those for the transceive command; see section 11.2.3 on page 85 . table 157. authent1 command 0ch command value action arguments and data returned data authent1 0ch performs the ?rst part of the crypto1 card authentication card authent1 command - card block address - card serial number lsb - card serial number byte1 - card serial number byte2 - card serial number msb - table 158. authent2 command 14h command value action arguments and data returned data authent2 14h performs the second part of the card authentication using the crypto1 algorithm --
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 99 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 11.7.4.1 authent2 command effects if the authent2 command is successful, the authenticity of card and the clrc632 are proved. this automatically sets the crypto1on control bit. when bit crypto1on = logic 1, all further card communication is encrypted using the crypto1 security algorithm. if the authent2 command fails, bit crypto1on is cleared (crypto1on = logic 0). remark: the crypto1on ?ag can only be set by a successfully executed authent2 command and not by the microprocessor. the microprocessor can clear bit crypto1on to continue with unencrypted (plain) card communication. remark: the authent2 command must be executed immediately after a successful authent1 command; see section 11.7.3 a uthent1 command 0ch . in addition, the keys stored in the key buffer and those on the card must match. 12. limiting values 13. characteristics 13.1 operating condition range table 159. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit t amb ambient temperature - 40 +150 c t stg storage temperature - 40 +150 c v ddd digital supply voltage - 0.5 +6 v v dda analog supply voltage - 0.5 +6 v v dd(tvdd) tvdd supply voltage - 0.5 +6 v | v i | input voltage (absolute value) on any digital pin to dvss - 0.5 v ddd + 0.5 v on pin rx to avss - 0.5 v dda + 0.5 v table 160. operating condition range symbol parameter conditions min typ max unit t amb ambient temperature - - 25 +25 +85 c v ddd digital supply voltage dvss = avss = tvss = 0 v 3.0 3.3 3.6 v 4.5 5.0 5.5 v v dda analog supply voltage dvss = avss = tvss = 0 v 4.5 5.0 5.5 v v dd(tvdd) tvdd supply voltage dvss = avss = tvss = 0 v 3.0 5.0 5.5 v v esd electrostatic discharge voltage human body model (hbm); 1.5 k w , 100 pf - - 1000 v machine model (mm); 0.75 m h, 200 pf - - 100 v
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 100 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 13.2 current consumption 13.3 pin characteristics 13.3.1 input pin characteristics pins d0 to d7, a0, and a1 have ttl input characteristics and behave as de?ned in t ab le 162 . the digital input pins ncs, nwr, nrd, ale, a2, and mfin have schmitt trigger characteristics, and behave as de?ned in t ab le 163 . table 161. current consumption symbol parameter conditions min typ max unit i ddd digital supply current idle command - 8 11 ma standby mode - 3 5 ma soft power-down mode - 800 1000 m a hard power-down mode - 1 10 m a i dda analog supply current idle command; receiver on - 25 40 ma idle command; receiver off - 12 15 ma standby mode - 10 13 ma soft power-down mode - 1 10 m a hard power-down mode - 1 10 m a i dd(tvdd) tvdd supply current continuous wave - - 150 ma pins tx1 and tx2 unconnected; tx1rfen and tx2rfen = logic 1 - 5.5 7 ma pins tx1 and tx2 unconnected; tx1rfen and tx2rfen = logic 0 - 65 130 m a table 162. standard input pin characteristics symbol parameter conditions min typ max unit i li input leakage current - 1.0 - +1.0 m a v th threshold voltage cmos: v ddd < 3.6 v 0.35v ddd - 0.65v ddd v ttl: 4.5 < v ddd 0.8 - 2.0 v table 163. schmitt trigger input pin characteristics symbol parameter conditions min typ max unit i li input leakage current - 1.0 - +1.0 m a v th threshold voltage positive-going threshold; ttl = 4.5 < v ddd 1.4 - 2.0 v cmos = v ddd < 3.6 v 0.65v ddd - 0.75v ddd v negative-going threshold; ttl = 4.5 < v ddd 0.8 - 1.3 v cmos = v ddd < 3.6 v 0.25v ddd - 0.4v ddd v
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 101 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) pin rstpd has schmitt trigger cmos characteristics. in addition, it is internally ?ltered by a rc low-pass ?lter which causes a propagation delay on the reset signal. the analog input pin rx has the input capacitance and input voltage range shown in t ab le 165 . 13.3.2 digital output pin characteristics pins d0 to d7, mfout and irq have cmos output characteristics and behave as de?ned in t ab le 166 . remark: pin irq can be con?gured as open collector which causes the v oh values to be no longer applicable. 13.3.3 antenna driver output pin characteristics the source conductance of the antenna driver pins tx1 and tx2 for driving the high-level can be con?gured using the cwconductance registers gscfgcw[5:0] bits, while their source conductance for driving the low-level is constant. the antenna driver default con?guration output characteristics are speci?ed in t ab le 167 . table 164. rstpd input pin characteristics symbol parameter conditions min typ max unit i li input leakage current - 1.0 - +1.0 m a v th threshold voltage positive-going threshold; cmos = v ddd < 3.6 v 0.65v ddd - 0.75v ddd v negative-going threshold; cmos = v ddd < 3.6 v 0.25v ddd - 0.4v ddd v t pd propagation delay - - 20 m s table 165. rx input capacitance and input voltage range symbol parameter conditions min typ max unit c i input capacitance - - 15 pf v i(dyn) dynamic input voltage v dda = 5 v; t amb = 25 c 1.1 - 4.4 v table 166. digital output pin characteristics symbol parameter conditions min typ max unit v oh high-level output voltage v ddd = 5 v; i oh = - 1 ma 2.4 4.9 - v v ddd = 5 v; i oh = - 10 ma 2.4 4.2 - v v ol low-level output voltage v ddd = 5 v; i ol = 1 ma - 25 400 mv v ddd = 5 v; i ol = 10 ma - 250 400 mv i o output current source or sink; v ddd =5v --10ma
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 102 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 13.4 ac electrical characteristics 13.4.1 separate read/write strobe bus timing table 167. antenna driver output pin characteristics symbol parameter conditions min typ max unit v oh high-level output voltage v dd(tvdd) = 5.0 v; i ol = 20 ma - 4.97 - v v dd(tvdd) = 5.0 v; i ol = 100 ma - 4.85 - v v ol low-level output voltage v dd(tvdd) = 5.0 v; i ol = 20 ma - 30 - mv v dd(tvdd) = 5.0 v; i ol = 100 ma - 150 - mv i o output current transmitter; continuous wave; peak-to-peak - - 200 ma table 168. timing speci?cation for separate read/write strobe symbol parameter conditions min typ max unit t lhll ale high time 20 - - ns t avll address valid to ale low time 15 - - ns t llax address hold after ale low time 8--ns t llrwl ale low to read/write low time ale low to nrd or nwr low 15 - - ns t slrwl chip select low to read/write low time ncs low to nrd or nwr low 0--ns t rwhsh read/write high to chip select high time nrd or nwr high to ncs high 0--ns t rldv read low to data input valid time nrd low to data valid - - 65 ns t rhdz read high to data input high impedance time nrd high to data high-impedance - - 20 ns t wlqv write low to data output valid time nwr low to data valid - - 35 ns t whdx data output hold after write high time data hold time after nwr high 8--ns t rwlrwh read/write low time nrd or nwr 65 - - ns t avrwl address valid to read/write low time nrd or nwr low (set-up time) 30 - - ns t whax address hold after write high time nwr high (hold time) 8 - - ns t rwhrwl read/write high time 150 - - ns
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 103 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) remark: the signal ale is not relevant for separate address/data bus and the multiplexed addresses on the data bus do not care. the multiplexed address and data bus address lines (a0 to a2) must be connected as described in section 9.1.3 on page 8 . 13.4.2 common read/write strobe bus timing fig 23. separate read/write strobe timing diagram 001aaj638 t slrwl t rwhsh t rwhrwl t whdx t rhdz t wlqv t rldv t avrwl t whax t llax t avll t rwlrwh t llrwl t rwhrwl t lhll a0 to a2 a0 to a2 d0 to d7 d0 to d7 nwr nrd ncs ale a0 to a2 multiplexed address bus separated address bus table 169. common read/write strobe timing speci?cation symbol parameter conditions min typ max unit t lhll ale high time 20 - - ns t avll address valid to ale low time 15 - - ns t llax address hold after ale low time 8 - - ns t lldsl ale low to data strobe low time nwr or nrd low 15--ns t sldsl chip select low to data strobe low time ncs low to nds low 0--ns t dshsh data strobe high to chip select high time 0--ns t dsldv data strobe low to data input valid time - - 65 ns t dshdz data strobe high to data input high impedance time - - 20 ns t dslqv data strobe low to data output valid time nds/ncs low - - 35 ns t dshqx data output hold after data strobe high time nds high (write cycle hold time) 8--ns t dshrwx rw hold after data strobe high time after nds high 8 - - ns t dsldsh data strobe low time nds/ncs 65 - - ns
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 104 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 13.4.3 epp bus timing t avdsl address valid to data strobe low time 30--ns t rhax address hold after read high time 8 - - ns t dshdsl data strobe high time period between write sequences 150 - - ns t wldsl write low to data strobe low time r/nw valid to nds low 8--ns fig 24. common read/write strobe timing diagram table 169. common read/write strobe timing speci?cation continued symbol parameter conditions min typ max unit 001aaj639 t sldsl t dshsh t dshdsl t dshqx t dshdz t dsldv t dslqv t avdsl t rhax t llax t avll t dsldsh t lldsl t dshdsl t lhll t wldsl t dshrwx a0 to a2 a0 to a2 d0 to d7 d0 to d7 nrd r/nw ncs/nds ale a0 to a2 multiplexed address bus separated address bus table 170. common read/write strobe timing speci?cation for epp symbol parameter conditions min typ max unit t aslash address strobe low time nastrb 20 - - ns t avash address valid to address strobe high time multiplexed address bus set-up time 15 - - ns t ashav address valid after address strobe high time multiplexed address bus hold time 8- - ns t sldsl chip select low to data strobe low time ncs low to ndstrb low 0- - ns t dshsh data strobe high to chip select high time ndstrb high to ncs high 0- - ns t dsldv data strobe low to data input valid time read cycle - - 65 ns
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 105 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) remark: figure 25 does not distinguish between the address write cycle and a data write cycle. the timings for the address write and data write cycle are different. in epp mode, the address lines (a0 to a2) must be connected as described in section 9.1.3 on page 8 . t dshdz data strobe high to data input high impedance time read cycle - - 20 ns t dslqv data strobe low to data output valid time ndstrb low - - 35 ns t dshqx data output hold after data strobe high time ncs high 8 - - ns t dshwx write hold after data strobe high time nwrite 8 - - ns t dsldsh data strobe low time ndstrb 65 - - ns t wldsl write low to data strobe low time nwrite valid to ndstrb low 8- - ns t dsl-waith data strobe low to wait high time ndstrb low to nwrite high - - 75 ns t dsh-waitl data strobe high to wait low time ndstrb high to nwrite low - - 75 ns fig 25. timing diagram for common read/write strobe; epp table 170. common read/write strobe timing speci?cation for epp continued symbol parameter conditions min typ max unit 001aaj640 nwait t dsl-waith t dsldv t dslqv t wldsl t sldsl t dshsh t dsldsh d0 to d7 a0 toa7 t dshqx t dshdz t dsh-waitl t dshwx d0 to d7 ndstrb nastrb nwrite ncs
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 106 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 13.4.4 spi timing remark: to send more bytes in one data stream the nss signal must be low during the send process. to send more than one data stream the nss signal must be high between each data stream. 13.4.5 clock frequency the clock input is pin oscin. the clock applied to the clrc632 acts as a time constant for the synchronous systems encoder and decoder. the stability of the clock frequency is an important factor for ensuring proper performance. to obtain highest performance, clock jitter must be as small as possible. this is best achieved using the internal oscillator buffer and the recommended circuitry; see section 9.8 on page 30 . table 171. spi timing speci?cation symbol parameter conditions min typ max unit t sckl sck low time 100 - - ns t sckh sck high time 100 - - ns t dshqx data output hold after data strobe high time 20--ns t dqxch data input/output changing to clock high time 20--ns t h(sckl-q) sck low to data output hold time - - 15 ns t (sckl-nssh) sck low to nss high time 20 - - ns fig 26. timing diagram for spi 001aaj641 t sckl t sckh t sckl t dqxch t dshqx t dqxch t h(sckl-q) t clsh sck mosi miso msb msb lsb lsb nss table 172. clock frequency symbol parameter conditions min typ max unit f clk clock frequency checked by the clock ?lter - 13.56 - mhz d clk clock duty cycle 40 50 60 % t jit jitter time of clock edges - - 10 ps
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 107 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 14. eeprom characteristics the eeprom size is 32 16 8 = 4096 bit. 15. application information 15.1 typical application 15.1.1 circuit diagram figure 27 shows a typical application where the antenna is directly matched to the clrc632: table 173. eeprom characteristics symbol parameter conditions min typ max unit n endu(w_er) write or erase endurance erase/write cycles 100.000 - - hz t ret retention time t amb 55 c 10 - - year t er erase time - - 2.9 ms t a(w) write access time - - 2.9 ms fig 27. application example circuit diagram: directly matched antenna 001aak625 dvdd rstpd avdd tvdd dvdd reset avdd tvdd dvss control lines data bus irq oscin oscout 13.56 mhz avss vmid rx tx2 tvss tx1 irq 15 pf 15 pf c0 c0 c2a c2b c3 r2 r1 l0 l0 c1 c1 c4 100 nf microprocessor bus microprocessor clrc632
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 108 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 15.1.2 circuit description the matching circuit consists of an emc low-pass ?lter (l0 and c0), matching circuitry (c1 and c2), a receiver circuit (r1, r2, c3 and c4) and the antenna itself. refer to the following application notes for more detailed information about designing and tuning an antenna. ? micore reader ic family; directly matched antenna design ref . 1 ? mifare (14443 a) 13.56 mhz rfid proximity antennas ref . 2 . 15.1.2.1 emc low-pass ?lter the mifare system operates at a frequency of 13.56 mhz. this frequency is generated by a quartz oscillator to clock the clrc632. it is also the basis for driving the antenna using the 13.56 mhz energy carrier. this not only causes power emissions at 13.56 mhz, it also emits power at higher harmonics. international emc regulations de?ne the amplitude of the emitted power over a broad frequency range. to meet these regulations, appropriate ?ltering of the output signal is required. a multilayer board is recommended to implement a low-pass ?lter as shown in figure 27 . the low-pass ?lter consists of the components l0 and c0. the recommended values are given in application notes micore reader ic family; directly matched antenna design ref . 1 and mifare (14443 a) 13.56 mhz rfid proximity antennas ref . 2 . remark: to achieve best performance, all components must be at least equal in quality to those recommended. remark: the layout has a major in?uence on the overall performance of the ?lter. 15.1.2.2 antenna matching due to the impedance transformation of the low-pass ?lter, the antenna coil has to be matched to a given impedance. the matching elements c1 and c2 can be estimated and have to be ?ne tuned depending on the design of the antenna coil. the correct impedance matching is important to ensure optimum performance. the overall quality factor has to be considered to guarantee a proper iso/iec 14443 a and iso/iec 14443 b communication schemes. environmental in?uences have to considered and common emc design rules. refer to application notes micore reader ic family; directly matched antenna design ref . 1 and mifare (14443 a) 13.56 mhz rfid proximity antennas ref . 2 for details. remark: do not exceed the current limits (i dd(tvdd) ), otherwise the chip might be destroyed. remark: the overall 13.56 mhz rfid proximity antenna design in combination with the clrc632 ic does not require any specialist rf knowledge. however, all relevant parameters have to be considered to guarantee optimum performance and international emc compliance. 15.1.2.3 receiver circuit the internal receiver of the clrc632 makes use of both subcarrier load modulation side-bands. no external ?ltering is required.
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 109 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) it is recommended to use the internally generated vmid potential as the input potential for pin rx. this vmid dc voltage level has to be coupled to pin rx using resistor (r2). to provide a stable dc reference voltage, a capacitor (c4) must be connected between vmid and ground. the ac voltage divider of r1 + c3 and r2 has to be designed taking in to account the ac voltage limits on pin rx. depending on the antenna coil design and the impedance, matching the voltage at the antenna coil will differ. therefore the recommended way to design the receiver circuit is to use the given values for r1, r2, and c3; refer to application note; mifare (14443 a) 13.56 mhz rfid proximity antennas ref . 2 . the voltage on pin rx can be altered by varying r1 within the given limits. remark: r2 is ac connected to ground using c4. 15.1.2.4 antenna coil the precise calculation of the antenna coils inductance is not practicable but the inductance can be estimated using equation 10 . we recommend designing an antenna that is either circular or rectangular. (10) ? l 1 = length of one turn of the conductor loop ? d 1 = diameter of the wire or width of the pcb conductor, respectively ? k = antenna shape factor (k = 1.07 for circular antennas and k = 1.47 for square antennas) ? n 1 = number of turns ? ln = natural logarithm function the values of the antenna inductance, resistance, and capacitance at 13.56 mhz depend on various parameters such as: ? antenna construction (type of pcb) ? thickness of conductor ? distance between the windings ? shielding layer ? metal or ferrite in the near environment therefore a measurement of these parameters under real life conditions or at least a rough measurement and a tuning procedure is highly recommended to guarantee a reasonable performance. refer to application notes micore reader ic family; directly matched antenna design ref . 1 and mifare (14443 a) 13.56 mhz rfid proximity antennas ref . 2 for details. l 1 nh [] 2 = i 1 cm [] i 1 d 1 ------ ? ln k C ? ?? n 1 1.8
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 110 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 15.2 test signals the clrc632 allows different kinds of signal measurements. these measurements can be used to check the internally generated and received signals using the serial signal switch as described in section 9.11 on page 37 . in addition, the clrc632 enables users to select between: ? internal analog signals for measurement on pin aux ? internal digital signals for observation on pin mfout (based on register selections) these measurements can be helpful during the design-in phase to optimize the receivers behavior, or for test purposes. 15.2.1 measurements using the serial signal switch using the serial signal switch on pin mfout, data is observed that is sent to the card or received from the card. t ab le 174 gives an overview of the different signals available. remark: the routing of the manchester or the manchester with subcarrier signal to pin mfout is only possible at 106 kbd based on iso/iec 14443 a. 15.2.1.1 tx control figure 28 shows as an example of an iso/iec 14443 a communication. the signal is measured on pin mfout using the serial signal switch to control the data sent to the card. setting the ?ag mfoutselect[2:0] = 3 sends the data to the card coded as nrz. setting mfoutselect[2:0] = 2 shows the data as a miller coded signal. the rfout signal is measured directly on the antenna and gives the rf signal pulse shape. refer to application note directly matched antenna - excel calculation ( ref . 3 )for detail information on the rf signal pulse. table 174. signal routed to pin mfout signaltomfout mfoutselect signal routed to pin mfout 00low 0 1 high 0 2 envelope 0 3 transmit nrz 0 4 manchester with subcarrier 0 5 manchester 0 6 reserved 0 7 reserved 1 x digital test signal
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 111 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 15.2.1.2 rx control figure 29 shows an example of iso/iec 14443 a communication which represents the beginning of a cards answer to a request signal. the rf signal shows the rf voltage measured directly on the antenna so that the cards load modulation is visible. setting mfoutselect[2:0] = 4 shows the manchester decoded signal with subcarrier. setting mfoutselect[2:0] = 5 shows the manchester decoded signal. (1) mfoutselect[2:0] = 3; serial data stream; 2 v per division. (2) mfoutselect[2:0] = 2; serial data stream; 2 v per division. (3) rfout; 1 v per division. fig 28. tx control signals 001aak626 (1) (2) (3) 10 m s per division
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 112 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 15.2.2 analog test signals the analog test signals can be routed to pin aux by selecting them using the testanaselect register testanaoutsel[4:0] bits. (1) rfout; 1 v per division. (2) mfoutselect[2:0] = 4; manchester with subcarrier; 2 v per division. (3) mfoutselect[2:0] = 5; manchester; 2 v per division. fig 29. rx control signals 001aak627 10 m s per division (1) (2) (3) table 175. analog test signal selection value signal name description 0 vmid voltage at internal node vmid 1 vbandgap internal reference voltage generated by the bandgap 2 vrxfolli output signal from the demodulator using the i-clock 3 vrxfollq output signal from the demodulator using the q-clock 4 vrxampi i-channel subcarrier signal ampli?ed and ?ltered 5 vrxampq q-channel subcarrier signal ampli?ed and ?ltered 6 vcorrni output signal of n-channel correlator fed by the i-channel subcarrier signal 7 vcorrnq output signal of n-channel correlator fed by the q-channel subcarrier signal 8 vcorrdi output signal of d-channel correlator fed by the i-channel subcarrier signal 9 vcorrdq output signal of d-channel correlator fed by the q-channel subcarrier signal a vevall evaluation signal from the left half-bit
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 113 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 15.2.3 digital test signals digital test signals can be routed to pin mfout by setting bit signaltomfout = logic 1. a digital test signal is selected using the testdigiselect register testdigisignalsel[6:0] bits. the signals selected by the testdigisignalsel[6:0] bits are shown in t ab le 176 . if test signals are not used, the testdigiselect register address value must be 00h. remark: all other values for testdigisignalsel[6:0] are for production test purposes only. 15.2.4 examples of iso/iec 14443 a analog and digital test signals figure 30 shows a mifare cards answer to a request command using the q-clock receiving path. rx reference is given to show the manchester modulated signal on pin rx. the signal is demodulated and ampli?ed in the receiver circuitry. signal vrxampq is the ampli?ed side-band signal using the q-clock for demodulation. the signals vcorrdq and vcorrnq were generated in the correlation circuitry. they are processed further in the evaluation and digitizer circuitry. b vevalr evaluation signal from the right half-bit c vtemp temperature voltage derived from band gap d reserved reserved for future use e reserved reserved for future use f reserved reserved for future use table 175. analog test signal selection continued value signal name description table 176. digital test signal selection testdigisignalsel [6:0] signal name description f4h s_data data received from the card e4h s_valid when logic 1 is returned the s_data and s_coll signals are valid d4h s_coll when logic 1 is returned a collision has been detected in the current bit c4h s_clock internal serial clock: during transmission, this is the encoder clock during reception this is the receiver clock b5h rd_sync internal synchronized read signal which is derived from the parallel microprocessor interface a5h wr_sync internal synchronized write signal which is derived from the parallel microprocessor interface 96h int_clock internal 13.56 mhz clock 83h bpsk_out bpsk output signal e2h bpsk_sig bpsk signals amplitude detected 00h no test signal output as de?ned by the mfoutselect register mfoutselect[2:0] bits routed to pin mfout
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 114 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) signals vevalr and vevall show the evaluation of the signals right and left half-bit. finally, the digital test signal s_data shows the received data. this is then sent to the internal digital circuit and s_valid which indicates the received data stream is valid. 15.2.5 examples of i-code1 analog and digital test signals figure 31 shows the answer of an i-code1 label ic to an unselected read command using the q-clock receiving path. rx reference is given to show the manchester modulated signal on pin rx. the signal is demodulated and ampli?ed in the receiver circuitry. signal vrxampq is the ampli?ed side-band signal using the q-clock for demodulation. the signals vcorrdq and vcorrnq generated in the correlation circuitry are processed further in the evaluation and digitizer circuitry. signals vevalr and vevall are the evaluation signal of the right and left half-bit. finally, the digital test-signal s_data shows the received data. this is then routed to the internal digital circuit and s_valid indicates that the received data stream is valid. fig 30. iso/iec 14443 a receiving path q-clock 001aak628 rx reference vrxampq vcorrdq vcorrnq vevalr vevall s_data s_valid 50 m s per division
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 115 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) fig 31. i-code1 receiving path q-clock vrxampq vcorrdq vcorrnq vevalr vevall s_data s_valid receiving path q-clock 50 m s per division 001aak629 500 m s per division
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 116 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 16. package outline fig 32. package outline sot287-1 unit a max. a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.1 0.25 0.01 1.4 0.055 0.3 0.1 2.45 2.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.2 1.0 0.95 0.55 8 0 o o 0.25 0.1 0.004 0.25 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot287-1 mo-119 (1) 0.012 0.004 0.096 0.089 0.02 0.01 0.05 0.047 0.039 0.419 0.394 0.30 0.29 0.81 0.80 0.011 0.007 0.037 0.022 0.01 0.01 0.043 0.016 w m b p d h e z e c v m a x a y 32 17 16 1 q a a 1 a 2 l p q detail x l (a ) 3 e pin 1 index 0 5 10 mm scale so32: plastic small outline package; 32 leads; body width 7.5 mm sot287-1 00-08-17 03-02-19
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 117 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 17. abbreviations 18. references [1] application note micore reader ic family; directly matched antenna design. [2] application note mifare (14443 a) 13.56 mhz rfid proximity antennas. [3] application note directly matched antenna - excel calculation. [4] iso standard iso/iec 14443 identi?cation cards - contactless integrated circuit(s) cards - proximity cards, part 1-4. [5] application note mifare implementation of higher baud rates. table 177. abbreviations and acronyms acronym description ask amplitude-shift keying bpsk binary phase-shift keying cmos complementary metal-oxide semiconductor crc cyclic redundancy check eof end of frame epp enhanced parallel port etu elementary time unit fifo first in, first out hbm human body model lsb least signi?cant bit mm machine model msb most signi?cant bit nrz none return to zero por power-on reset pcd proximity coupling device picc proximity integrated circuit card sof start of frame spi serial peripheral interface
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 118 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 19. revision history table 178. revision history document id release date data sheet status change notice supersedes clrc632_35 20091110 product data sheet - clrc632_34 modi?cations: ? data sheet security status changed from company confidential to company public ? ratp/innovatron technologies license statement added to the legal page clrc632_34 20091014 product data sheet - 073933 modi?cations: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors ? legal texts have been adapted to the new company name where appropriate ? the symbols for electrical characteristics and their parameters have been updated to meet the nxp semiconductors guidelines ? a number of inconsistencies in pin, register and bit names have been eliminated from the data sheet ? all drawings have been updated ? several symbol changes made to drawings in figure 23 on page 103 to figure 26 on page 106 ? section 5 quick reference data on page 3: section added ? section 6 ordering information on page 3: updated ? section 15.1.2.4 antenna coil on page 109: added missing formula and updated the last clause ? section 16 package outline on page 116: updated ? section 18 references on page 117: added section and updated the references in the document 073933 december 2005 product data sheet 073932 073932 april 2005 product data sheet 073931 073931 may 2004 product data sheet 073930 073930 november 2002 product data sheet 073920 073920 june 2002 preliminary data sheet 073910 073910 january 2002 internal version -
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 119 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 20.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 20.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. quick reference data the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 20.4 licenses 20.5 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. mifare is a trademark of nxp b.v. mifare ultralight is a trademark of nxp b.v. i-code is a trademark of nxp b.v. document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation. purchase of nxp ics with iso/iec 14443 type b functionality this nxp semiconductors ic is iso/iec 14443 type b software enabled and is licensed under innovatrons contactless card patents license for iso/iec 14443 b. the license includes the right to use the ic in systems and/or end-user equipment. ratp/innovatron technology
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 120 of 126 nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 21. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 121 of 126 continued >> nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 22. tables table 1. quick reference data . . . . . . . . . . . . . . . . . . . . .3 table 2. ordering information . . . . . . . . . . . . . . . . . . . . .3 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 4. supported microprocessor and epp interface signals . . . . . . . . . . . . . . . . . . . . . . . . .7 table 5. connection scheme for detecting the parallel interface type . . . . . . . . . . . . . . . . . . . . .8 table 6. spi compatibility . . . . . . . . . . . . . . . . . . . . . . .10 table 7. spi read data . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 8. spi read address . . . . . . . . . . . . . . . . . . . . . . .11 table 9. spi write data . . . . . . . . . . . . . . . . . . . . . . . . .11 table 10. spi write address . . . . . . . . . . . . . . . . . . . . . .11 table 11. eeprom memory organization diagram . . . . .12 table 12. product information ?eld . . . . . . . . . . . . . . . . .13 table 13. product type identi?cation de?nition . . . . . . . .13 table 14. byte assignment for register initialization at start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 15. shipment content of startup con?guration ?le 15 table 16. byte assignment for register initialization at startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 17. content of i-code1 startup con?guration . . . .17 table 18. fifo buffer access . . . . . . . . . . . . . . . . . . . . .19 table 19. associated fifo buffer registers and ?ags . . .20 table 20. interrupt sources . . . . . . . . . . . . . . . . . . . . . . .21 table 21. interrupt control registers . . . . . . . . . . . . . . . .21 table 22. associated interrupt request system registers and ?ags . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 23. timeslotperiod . . . . . . . . . . . . . . . . . . . . . . . .26 table 24. associated timer unit registers and ?ags . . . . .27 table 25. signal on pins during hard power-down . . . . .28 table 26. pin tx1 con?gurations . . . . . . . . . . . . . . . . . . .31 table 27. pin tx2 con?gurations . . . . . . . . . . . . . . . . . . .32 table 28. tx1 and tx2 source resistance of n-channel driver transistor against gscfgcw or gscfgmod . . . . . . . . . . . . . . . . .33 table 29. gain factors for the internal ampli?er . . . . . . . .36 table 30. decodersource[1:0] values . . . . . . . . . . . . . . .39 table 31. modulatorsource[1:0] values . . . . . . . . . . . . . .39 table 32. mfoutselect[2:0] values . . . . . . . . . . . . . . . .39 table 33. register settings to enable use of the analog circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 34. mifare higher baud rates . . . . . . . . . . . . . . .40 table 35. iso/iec 14443 b registers and ?ags . . . . . . . .41 table 36. dedicated address bus: assembling the register address . . . . . . . . . . . . . . . . . . . . . . . .43 table 37. multiplexed address bus: assembling the register address . . . . . . . . . . . . . . . . . . . . . . . .44 table 38. behavior and designation of register bits . . . . .44 table 39. clrc632 register overview . . . . . . . . . . . . . . 45 table 40. clrc632 register ?ags overview . . . . . . . . . . 47 table 41. page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h) reset value: 1000 0000b, 80h bit allocation . . . . . . . . . . . . 50 table 42. page register bit descriptions . . . . . . . . . . . . . 50 table 43. command register (address: 01h) reset value: x000 0000b, x0h bit allocation . . . 50 table 44. command register bit descriptions . . . . . . . . . 50 table 45. fifodata register (address: 02h) reset value: xxxx xxxxb, 05h bit allocation . . . 51 table 46. fifodata register bit descriptions . . . . . . . . . 51 table 47. primarystatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation . . . 51 table 48. primarystatus register bit descriptions . . . . . . 51 table 49. fifolength register (address: 04h) reset value: 0000 0000b, 00h bit allocation . . . 52 table 50. fifolength bit descriptions . . . . . . . . . . . . . . 52 table 51. secondarystatus register (address: 05h) reset value: 01100 000b, 60h bit allocation . . . 53 table 52. secondarystatus register bit descriptions . . . . 53 table 53. interrupten register (address: 06h) reset value: 0000 0000b, 00h bit allocation . . . 53 table 54. interrupten register bit descriptions . . . . . . . . 53 table 55. interruptrq register (address: 07h) reset value: 0000 0000b, 00h bit allocation . . . 54 table 56. interruptrq register bit descriptions . . . . . . . . 54 table 57. control register (address: 09h) reset value: 0000 0000b, 00h bit allocation . . . 55 table 58. control register bit descriptions . . . . . . . . . . . . 55 table 59. errorflag register (address: 0ah) reset value: 0100 0000b, 40h bit allocation . . . 55 table 60. errorflag register bit descriptions . . . . . . . . . . 55 table 61. collpos register (address: 0bh) reset value: 0000 0000b, 00h bit allocation . . . 56 table 62. collpos register bit descriptions . . . . . . . . . . . 56 table 63. timervalue register (address: 0ch) reset value: xxxx xxxxb, xxh bit allocation . . . . 57 table 64. timervalue register bit descriptions . . . . . . . . 57 table 65. crcresultlsb register (address: 0dh) reset value: xxxx xxxxb, xxh bit allocation . . . . 57 table 66. crcresultlsb register bit descriptions . . . . . 57 table 67. crcresultmsb register (address: 0eh) reset value: xxxx xxxxb, xxh bit allocation . . . . 57 table 68. crcresultmsb register bit descriptions . . . . 57 table 69. bitframing register (address: 0fh) reset value: 0000 0000b, 00h bit allocation . . . 58 table 70. bitframing register bit descriptions . . . . . . . . . 58
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 122 of 126 continued >> nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) table 71. txcontrol register (address: 11h) reset value: 0101 1000b, 58h bit allocation . . .59 table 72. txcontrol register bit descriptions . . . . . . . . . .59 table 73. cwconductance register (address: 12h) reset value: 0011 1111b, 3fh bit allocation . . .60 table 74. cwconductance register bit descriptions . . . .60 table 75. modconductance register (address: 13h) reset value: 0011 1111b, 3fh bit allocation . . .60 table 76. modconductance register bit descriptions . . . .60 table 77. codercontrol register (address: 14h) reset value: 0001 1001b, 19h bit allocation . . .61 table 78. codercontrol register bit descriptions . . . . . . .61 table 79. modwidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation . . .62 table 80. modwidth register bit descriptions . . . . . . . . . .62 table 81. modwidthsof register (address: 16h) reset value: 0011 1111b, 3fh bit allocation . . .62 table 82. modwidthsof register bit descriptions . . . . . .62 table 83. typebframing register (address: 17h) reset value: 0011 1011b, 3bh bit allocation . . .63 table 84. typebframing register bit descriptions . . . . . .63 table 85. rxcontrol1 register (address: 19h) reset value: 0111 0011b, 73h bit allocation . . .64 table 86. rxcontrol1 register bit descriptions . . . . . . . . .64 table 87. decodercontrol register (address: 1ah) reset value: 0000 1000b, 08h bit allocation . . .65 table 88. decodercontrol register bit descriptions . . . . .65 table 89. bitphase register (address: 1bh) reset value: 1010 1101b, adh bit allocation . .65 table 90. bitphase register bit descriptions . . . . . . . . . .65 table 91. rxthreshold register (address: 1ch) reset value: 1111 1111b, ffh bit allocation . . .66 table 92. rxthreshold register bit descriptions . . . . . . .66 table 93. bpskdemcontrol register (address: 1dh) reset value: 0001 1110b, 1eh bit allocation . . .66 table 94. bpskdemcontrol register bit descriptions . . .66 table 95. rxcontrol2 register (address: 1eh) reset value: 0100 0001b, 41h bit allocation . . .67 table 96. rxcontrol2 register bit descriptions . . . . . . . . .67 table 97. clockqcontrol register (address: 1fh) reset value: 000x xxxxb, xxh bit allocation . . . .67 table 98. clockqcontrol register bit descriptions . . . . . .67 table 99. rxwait register (address: 21h) reset value: 0000 0101b, 06h bit allocation . . .68 table 100.rxwait register bit descriptions . . . . . . . . . . . .68 table 101.channelredundancy register (address: 22h) reset value: 0000 0011b, 03h bit allocation . . .68 table 102.channelredundancy bit descriptions . . . . . . .68 table 103.crcpresetlsb register (address: 23h) reset value: 0101 0011b, 63h bit allocation . . .69 table 104.crcpresetlsb register bit descriptions . . . . .69 table 105.crcpresetmsb register (address: 24h) reset value: 0101 0011b, 63h bit allocation . . . 69 table 106.crcpresetmsb bit descriptions . . . . . . . . . . . 69 table 107.timeslotperiod register (address: 25h) reset value: 0000 0000b, 00h bit allocation . . . 69 table 108.timeslotperiod register bit descriptions . . . . . 70 table 109.mfoutselect register (address: 26h) reset value: 0000 0000b, 00h bit allocation . . . 70 table 110.mfoutselect register bit descriptions . . . . . . 70 table 111.preset27 (address: 27h) reset value: xxxx xxxxb, xxh bit allocation . . . . 70 table 112.fifolevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation . . . 71 table 113.fifolevel register bit descriptions . . . . . . . . . 71 table 114.timerclock register (address: 2ah) reset value: 0000 0111b, 07h bit allocation . . . 71 table 115.timerclock register bit descriptions . . . . . . . . 71 table 116.timercontrol register (address: 2bh) reset value: 0000 0110b, 06h bit allocation . . . 72 table 117.timercontrol register bit descriptions . . . . . . . 72 table 118.timerreload register (address: 2ch) reset value: 0000 1010b, 0ah bit allocation . . 72 table 119.timerreload register bit descriptions . . . . . . . 72 table 120.irqpincon?g register (address: 2dh) reset value: 0000 0010b, 02h bit allocation . . . 73 table 121.irqpincon?g register bit descriptions . . . . . . 73 table 122.preset2e register (address: 2eh) reset value: xxxx xxxxb, xxh bit allocation . . . . 73 table 123.preset2f register (address: 2fh) reset value: xxxx xxxxb, xxh bit allocation . . . . 73 table 124.reserved registers (address: 31h, 32h, 33h, 34h, 35h, 36h, 37h) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 73 table 125.reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation . . . . 74 table 126.testanaselect register (address: 3ah) reset value: 0000 0000b, 00h bit allocation . . . 74 table 127.testanaselect bit descriptions . . . . . . . . . . . . 74 table 128.reserved register (address: 3bh) reset value: xxxx xxxxb, xxh bit allocation . . . . 75 table 129.reserved register (address: 3ch) reset value: xxxx xxxxb, xxh bit allocation . . . . 75 table 130.testdigiselect register (address: 3dh) reset value: xxxx xxxxb, xxh bit allocation . . . . 75 table 131.testdigiselect register bit descriptions . . . . . . 75 table 132.reserved register (address: 3eh, 3fh) reset value: xxxx xxxxb, xxh bit allocation . . . . 76 table 133.clrc632 commands overview . . . . . . . . . . . . 76 table 134.startup command 3fh . . . . . . . . . . . . . . . . . . 78 table 135.idle command 00h . . . . . . . . . . . . . . . . . . . . . . 78 table 136.transmit command 1ah . . . . . . . . . . . . . . . . . 79
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 123 of 126 continued >> nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) table 137.transmission of frames of more than 64 bytes 82 table 138.receive command 16h . . . . . . . . . . . . . . . . . .82 table 139.return values for bit-collision positions . . . . . .84 table 140.communication error table . . . . . . . . . . . . . . .84 table 141.transceive command 1eh . . . . . . . . . . . . . . . .85 table 142.meaning of modemstate . . . . . . . . . . . . . . . . .85 table 143.transmit command 1ah . . . . . . . . . . . . . . . . . .87 table 144.receive command 16h . . . . . . . . . . . . . . . . . .88 table 145.return values for bit-collision positions . . . . . .90 table 146.communication error table . . . . . . . . . . . . . . .90 table 147.transceive command 1eh . . . . . . . . . . . . . . . .91 table 148. modemstate values . . . . . . . . . . . . . . . . . . . .91 table 149.writee2 command 01h . . . . . . . . . . . . . . . . . .93 table 150.reade2 command 03h . . . . . . . . . . . . . . . . . .95 table 151.loadcon?g command 07h . . . . . . . . . . . . . . . .95 table 152.calccrc command 12h . . . . . . . . . . . . . . . . .96 table 153.crc coprocessor parameters . . . . . . . . . . . . .96 table 154.errorflag register error ?ags overview . . . . . .97 table 155.loadkeye2 command 0bh . . . . . . . . . . . . . . .97 table 156.loadkey command 19h . . . . . . . . . . . . . . . . . .97 table 157.authent1 command 0ch . . . . . . . . . . . . . . . . .98 table 158.authent2 command 14h . . . . . . . . . . . . . . . . . .98 table 159.limiting values . . . . . . . . . . . . . . . . . . . . . . . . .99 table 160.operating condition range . . . . . . . . . . . . . . . . 99 table 161.current consumption . . . . . . . . . . . . . . . . . . . 100 table 162.standard input pin characteristics . . . . . . . . . 100 table 163.schmitt trigger input pin characteristics . . . . 100 table 164.rstpd input pin characteristics . . . . . . . . . . 101 table 165.rx input capacitance and input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 166.digital output pin characteristics . . . . . . . . . . 101 table 167.antenna driver output pin characteristics . . . 102 table 168.timing speci?cation for separate read/write strobe . . . . . . . . . . . . . . . . . . . . . . 102 table 169.common read/write strobe timing speci?cation . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 170.common read/write strobe timing speci?cation for epp . . . . . . . . . . . . . . . . . . . 104 table 171.spi timing speci?cation . . . . . . . . . . . . . . . . . 106 table 172.clock frequency . . . . . . . . . . . . . . . . . . . . . . 106 table 173.eeprom characteristics . . . . . . . . . . . . . . . . 107 table 174.signal routed to pin mfout . . . . . . . . . . . . . 110 table 175.analog test signal selection . . . . . . . . . . . . . . 112 table 176.digital test signal selection . . . . . . . . . . . . . . 113 table 177.abbreviations and acronyms . . . . . . . . . . . . . 117 table 178.revision history . . . . . . . . . . . . . . . . . . . . . . . 118 23. figures fig 1. clrc632 block diagram . . . . . . . . . . . . . . . . . . . .4 fig 2. clrc632 pin con?guration . . . . . . . . . . . . . . . . . .5 fig 3. connection to microprocessor: separate read and write strobes . . . . . . . . . . . . . . . . . . . . . .8 fig 4. connection to microprocessor: common read and write strobes . . . . . . . . . . . . . . . . . . . . . .9 fig 5. connection to microprocessor: epp common read/write strobes and handshake. . . . . . . . . . . . .9 fig 6. connection to microprocessor: spi . . . . . . . . . . .10 fig 7. key storage format. . . . . . . . . . . . . . . . . . . . . . . .18 fig 8. timer module block diagram . . . . . . . . . . . . . . . .24 fig 9. timeslotperiod . . . . . . . . . . . . . . . . . . . . . . . . . .26 fig 10. the startup procedure . . . . . . . . . . . . . . . . . . . .29 fig 11. quartz clock connection . . . . . . . . . . . . . . . . . . .30 fig 12. receiver circuit block diagram . . . . . . . . . . . . . . .35 fig 13. automatic q-clock calibration. . . . . . . . . . . . . . . .36 fig 14. serial signal switch block diagram . . . . . . . . . . . .38 fig 15. crypto1 key handling block diagram . . . . . . . . . .42 fig 16. transmitting bit oriented frames. . . . . . . . . . . . . .80 fig 17. timing for transmitting byte oriented frames . . . .81 fig 18. timing for transmitting bit oriented frames. . . . . .81 fig 19. card communication state diagram . . . . . . . . . . .86 fig 20. timing for transmitting byte oriented frames . . . .88 fig 21. label communication state diagram . . . . . . . . . .92 fig 22. eeprom programming timing diagram . . . . . . . 94 fig 23. separate read/write strobe timing diagram . . . . 103 fig 24. common read/write strobe timing diagram . . . . 104 fig 25. timing diagram for common read/write strobe; epp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 fig 26. timing diagram for spi . . . . . . . . . . . . . . . . . . . 106 fig 27. application example circuit diagram: directly matched antenna. . . . . . . . . . . . . . . . . . . . . . . . 107 fig 28. tx control signals . . . . . . . . . . . . . . . . . . . . . . . 111 fig 29. rx control signals . . . . . . . . . . . . . . . . . . . . . . . 112 fig 30. iso/iec 14443 a receiving path q-clock . . . . . 114 fig 31. i-code1 receiving path q-clock . . . . . . . . . . . . 115 fig 32. package outline sot287-1 . . . . . . . . . . . . . . . . 116
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 124 of 126 continued >> nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 24. contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 general description . . . . . . . . . . . . . . . . . . . . . . 1 3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 quick reference data . . . . . . . . . . . . . . . . . . . . . 3 6 ordering information . . . . . . . . . . . . . . . . . . . . . 3 7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 8.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 functional description . . . . . . . . . . . . . . . . . . . 7 9.1 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.1 overview of supported microprocessor interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.2 automatic microprocessor interface detection . 7 9.1.3 connection to different microprocessor types . 8 9.1.3.1 separate read and write strobe . . . . . . . . . . . . 8 9.1.3.2 common read and write strobe . . . . . . . . . . . . 9 9.1.3.3 common read and write strobe: epp with handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9.1.4 serial peripheral interface . . . . . . . . . . . . . . . . 9 9.1.4.1 spi read data . . . . . . . . . . . . . . . . . . . . . . . . . 10 9.1.4.2 spi write data . . . . . . . . . . . . . . . . . . . . . . . . . 11 9.2 memory organization of the eeprom . . . . . . 12 9.2.1 product information ?eld (read only). . . . . . . . 13 9.2.2 register initialization ?les (read/write) . . . . . . 13 9.2.2.1 startup register initialization ?le (read/write) . 14 9.2.2.2 factory default startup register initialization ?le . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9.2.2.3 register initialization ?le (read/write) . . . . . . . 16 9.2.2.4 content of i-code1 and iso/iec 15693 startup register values . . . . . . . . . . . . . . . . . . 16 9.2.3 crypto1 keys (write only) . . . . . . . . . . . . . . . . 18 9.2.3.1 key format. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.2.3.2 storage of keys in the eeprom. . . . . . . . . . . 18 9.3 fifo buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.3.1 accessing the fifo buffer . . . . . . . . . . . . . . . 19 9.3.1.1 access rules . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.3.2 controlling the fifo buffer . . . . . . . . . . . . . . . 19 9.3.3 fifo buffer status information . . . . . . . . . . . . 20 9.3.4 fifo buffer registers and ?ags . . . . . . . . . . . . 20 9.4 interrupt request system . . . . . . . . . . . . . . . . . 20 9.4.1 interrupt sources overview . . . . . . . . . . . . . . . 21 9.4.2 interrupt request handling. . . . . . . . . . . . . . . . 21 9.4.2.1 controlling interrupts and getting their status . 21 9.4.2.2 accessing the interrupt registers . . . . . . . . . . 22 9.4.3 con?guration of pin irq. . . . . . . . . . . . . . . . . 22 9.4.4 register overview interrupt request system . . 23 9.5 timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.5.1 timer unit implementation . . . . . . . . . . . . . . . 24 9.5.1.1 timer unit block diagram . . . . . . . . . . . . . . . . 24 9.5.1.2 controlling the timer unit . . . . . . . . . . . . . . . . 24 9.5.1.3 timer unit clock and period . . . . . . . . . . . . . . 25 9.5.1.4 timer unit status. . . . . . . . . . . . . . . . . . . . . . . 25 9.5.1.5 timeslotperiod. . . . . . . . . . . . . . . . . . . . . . . . 26 9.5.2 using the timer unit functions. . . . . . . . . . . . . 27 9.5.2.1 time-out and watchdog counters . . . . . . . . . 27 9.5.2.2 stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.5.2.3 programmable one shot timer and periodic trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.5.3 timer unit registers . . . . . . . . . . . . . . . . . . . . 27 9.6 power reduction modes . . . . . . . . . . . . . . . . . 28 9.6.1 hard power-down . . . . . . . . . . . . . . . . . . . . . . 28 9.6.2 soft power-down mode . . . . . . . . . . . . . . . . . 28 9.6.3 standby mode . . . . . . . . . . . . . . . . . . . . . . . . 29 9.6.4 automatic receiver power-down . . . . . . . . . . . 29 9.7 startup phase . . . . . . . . . . . . . . . . . . . . . . . . 29 9.7.1 hard power-down phase . . . . . . . . . . . . . . . . 29 9.7.2 reset phase . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.7.3 initialization phase . . . . . . . . . . . . . . . . . . . . . 30 9.7.4 initializing the parallel interface type . . . . . . . 30 9.8 oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . 30 9.9 transmitter pins tx1 and tx2 . . . . . . . . . . . . 31 9.9.1 con?guring pins tx1 and tx2 . . . . . . . . . . . . 31 9.9.2 antenna operating distance versus power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.9.3 antenna driver output source resistance . . . . 32 9.9.3.1 source resistance table . . . . . . . . . . . . . . . . . 33 9.9.3.2 calculating the relative source resistance . . . 34 9.9.3.3 calculating the effective source resistance . . 34 9.9.4 pulse width. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.10 receiver circuitry . . . . . . . . . . . . . . . . . . . . . . 34 9.10.1 receiver circuit block diagram . . . . . . . . . . . . 35 9.10.2 receiver operation . . . . . . . . . . . . . . . . . . . . . 35 9.10.2.1 automatic q-clock calibration. . . . . . . . . . . . . 35 9.10.2.2 ampli?er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.10.2.3 correlation circuitry . . . . . . . . . . . . . . . . . . . . 37 9.10.2.4 evaluation and digitizer circuitry. . . . . . . . . . . 37 9.11 serial signal switch. . . . . . . . . . . . . . . . . . . . . 37 9.11.1 serial signal switch block diagram . . . . . . . . . 38 9.11.2 serial signal switch registers . . . . . . . . . . . . . 38 9.11.2.1 active antenna concept . . . . . . . . . . . . . . . . . 39 9.11.2.2 driving both rf parts . . . . . . . . . . . . . . . . . . . 40 9.12 mifare higher baud rates . . . . . . . . . . . . . . . 40
clrc632_35 ? nxp b.v. 2009. all rights reserved. product data sheet public rev. 3.5 10 november 2009 073935 125 of 126 continued >> nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) 9.13 iso/iec 14443 b communication scheme . . . 41 9.14 mifare authentication and crypto1 . . . . . . . 42 9.14.1 crypto1 key handling . . . . . . . . . . . . . . . . . . . 42 9.14.2 authentication procedure . . . . . . . . . . . . . . . . 43 10 clrc632 registers. . . . . . . . . . . . . . . . . . . . . . 43 10.1 register addressing modes . . . . . . . . . . . . . . 43 10.1.1 page registers. . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.2 dedicated address bus . . . . . . . . . . . . . . . . . . 43 10.1.3 multiplexed address bus . . . . . . . . . . . . . . . . . 43 10.2 register bit behavior. . . . . . . . . . . . . . . . . . . . 44 10.3 register overview . . . . . . . . . . . . . . . . . . . . . . 45 10.4 clrc632 register ?ags overview . . . . . . . . . . 46 10.5 register descriptions . . . . . . . . . . . . . . . . . . . 50 10.5.1 page 0: command and status . . . . . . . . . . . . 50 10.5.1.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.5.1.2 command register . . . . . . . . . . . . . . . . . . . . . 50 10.5.1.3 fifodata register . . . . . . . . . . . . . . . . . . . . . . 51 10.5.1.4 primarystatus register . . . . . . . . . . . . . . . . . . 51 10.5.1.5 fifolength register . . . . . . . . . . . . . . . . . . . . 52 10.5.1.6 secondarystatus register . . . . . . . . . . . . . . . . 53 10.5.1.7 interrupten register . . . . . . . . . . . . . . . . . . . . . 53 10.5.1.8 interruptrq register. . . . . . . . . . . . . . . . . . . . . 54 10.5.2 page 1: control and status . . . . . . . . . . . . . . . 55 10.5.2.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.5.2.2 control register . . . . . . . . . . . . . . . . . . . . . . . . 55 10.5.2.3 errorflag register . . . . . . . . . . . . . . . . . . . . . . 55 10.5.2.4 collpos register. . . . . . . . . . . . . . . . . . . . . . . . 56 10.5.2.5 timervalue register. . . . . . . . . . . . . . . . . . . . . 57 10.5.2.6 crcresultlsb register . . . . . . . . . . . . . . . . . 57 10.5.2.7 crcresultmsb register . . . . . . . . . . . . . . . . . 57 10.5.2.8 bitframing register . . . . . . . . . . . . . . . . . . . . . 58 10.5.3 page 2: transmitter and control . . . . . . . . . . . 59 10.5.3.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.5.3.2 txcontrol register . . . . . . . . . . . . . . . . . . . . . . 59 10.5.3.3 cwconductance register . . . . . . . . . . . . . . . . 60 10.5.3.4 modconductance register. . . . . . . . . . . . . . . . 60 10.5.3.5 codercontrol register . . . . . . . . . . . . . . . . . . . 61 10.5.3.6 modwidth register. . . . . . . . . . . . . . . . . . . . . . 62 10.5.3.7 modwidthsof register . . . . . . . . . . . . . . . . . . 62 10.5.3.8 typebframing. . . . . . . . . . . . . . . . . . . . . . . . . 63 10.5.4 page 3: receiver and decoder control . . . . . . 64 10.5.4.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.5.4.2 rxcontrol1 register. . . . . . . . . . . . . . . . . . . . . 64 10.5.4.3 decodercontrol register . . . . . . . . . . . . . . . . . 65 10.5.4.4 bitphase register . . . . . . . . . . . . . . . . . . . . . . 65 10.5.4.5 rxthreshold register . . . . . . . . . . . . . . . . . . . 66 10.5.4.6 bpskdemcontrol . . . . . . . . . . . . . . . . . . . . . . 66 10.5.4.7 rxcontrol2 register. . . . . . . . . . . . . . . . . . . . . 67 10.5.4.8 clockqcontrol register . . . . . . . . . . . . . . . . . . 67 10.5.5 page 4: rf timing and channel redundancy . 68 10.5.5.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.5.5.2 rxwait register. . . . . . . . . . . . . . . . . . . . . . . . 68 10.5.5.3 channelredundancy register. . . . . . . . . . . . . 68 10.5.5.4 crcpresetlsb register . . . . . . . . . . . . . . . . . 69 10.5.5.5 crcpresetmsb register . . . . . . . . . . . . . . . . 69 10.5.5.6 timeslotperiod register . . . . . . . . . . . . . . . . . 69 10.5.5.7 mfoutselect register . . . . . . . . . . . . . . . . . . 70 10.5.5.8 preset27 register . . . . . . . . . . . . . . . . . . . . . . 70 10.5.6 page 5: fifo, timer and irq pin con?guration 71 10.5.6.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.5.6.2 fifolevel register . . . . . . . . . . . . . . . . . . . . . 71 10.5.6.3 timerclock register . . . . . . . . . . . . . . . . . . . . 71 10.5.6.4 timercontrol register . . . . . . . . . . . . . . . . . . . 72 10.5.6.5 timerreload register . . . . . . . . . . . . . . . . . . . 72 10.5.6.6 irqpincon?g register . . . . . . . . . . . . . . . . . . 73 10.5.6.7 preset2e register. . . . . . . . . . . . . . . . . . . . . . 73 10.5.6.8 preset2f register . . . . . . . . . . . . . . . . . . . . . . 73 10.5.7 page 6: reserved . . . . . . . . . . . . . . . . . . . . . . 73 10.5.7.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.5.7.2 reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h . . . . . . . . . . . . . . . . . . . . . . 73 10.5.8 page 7: test control . . . . . . . . . . . . . . . . . . . . 74 10.5.8.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.5.8.2 reserved register 39h . . . . . . . . . . . . . . . . . . 74 10.5.8.3 testanaselect register . . . . . . . . . . . . . . . . . . 74 10.5.8.4 reserved register 3bh . . . . . . . . . . . . . . . . . . 75 10.5.8.5 reserved register 3ch . . . . . . . . . . . . . . . . . . 75 10.5.8.6 testdigiselect register . . . . . . . . . . . . . . . . . . 75 10.5.8.7 reserved registers 3eh, 3fh . . . . . . . . . . . . . 76 11 clrc632 command set . . . . . . . . . . . . . . . . . 76 11.1 clrc632 command overview . . . . . . . . . . . . 76 11.1.1 basic states . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.1.2 startup command 3fh . . . . . . . . . . . . . . . . . . 78 11.1.3 idle command 00h . . . . . . . . . . . . . . . . . . . . . 78 11.2 commands for iso/iec 14443 a card communication . . . . . . . . . . . . . . . . . . . . . . . . 79 11.2.1 transmit command 1ah . . . . . . . . . . . . . . . . . 79 11.2.1.1 using the transmit command. . . . . . . . . . . . . 79 11.2.1.2 rf channel redundancy and framing . . . . . . . 80 11.2.1.3 transmission of bit oriented frames . . . . . . . . 80 11.2.1.4 transmission of frames with more than 64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.2.2 receive command 16h. . . . . . . . . . . . . . . . . . 82 11.2.2.1 using the receive command . . . . . . . . . . . . . 82 11.2.2.2 rf channel redundancy and framing . . . . . . . 82 11.2.2.3 collision detection . . . . . . . . . . . . . . . . . . . . . 83 11.2.2.4 receiving bit oriented frames. . . . . . . . . . . . . 84 11.2.2.5 communication errors . . . . . . . . . . . . . . . . . . 84 11.2.3 transceive command 1eh . . . . . . . . . . . . . . . 85 11.2.4 states of the card communication . . . . . . . . . 85
nxp semiconductors clrc632 multiple protocol contactless reader ic (mifare/i-code1) ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 10 november 2009 073935 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 11.2.5 card communication state diagram . . . . . . . . 86 11.3 i-code1 and iso/iec 15693 label communication commands . . . . . . . . . . . . . . . 87 11.3.1 transmit command 1ah . . . . . . . . . . . . . . . . . 87 11.3.1.1 using the transmit command . . . . . . . . . . . . . 87 11.3.1.2 rf channel redundancy and framing . . . . . . . 88 11.3.1.3 transmission of frames of more than 64 bytes 88 11.3.2 receive command 16h . . . . . . . . . . . . . . . . . . 88 11.3.2.1 using the receive command . . . . . . . . . . . . . 89 11.3.2.2 rf channel redundancy and framing . . . . . . . 89 11.3.2.3 collision detection. . . . . . . . . . . . . . . . . . . . . . 89 11.3.2.4 communication errors . . . . . . . . . . . . . . . . . . 90 11.3.3 transceive command 1eh. . . . . . . . . . . . . . . . 91 11.3.4 label communication states . . . . . . . . . . . . . . 91 11.3.5 label communication state diagram . . . . . . . . 92 11.4 eeprom commands . . . . . . . . . . . . . . . . . . . 93 11.4.1 writee2 command 01h . . . . . . . . . . . . . . . . . . 93 11.4.1.1 programming process. . . . . . . . . . . . . . . . . . . 93 11.4.1.2 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . 94 11.4.1.3 writee2 command error ?ags . . . . . . . . . . . . . 94 11.4.2 reade2 command 03h . . . . . . . . . . . . . . . . . . 95 11.4.2.1 reade2 command error ?ags. . . . . . . . . . . . . 95 11.5 diverse commands . . . . . . . . . . . . . . . . . . . . . 95 11.5.1 loadcon?g command 07h . . . . . . . . . . . . . . . 95 11.5.1.1 register assignment . . . . . . . . . . . . . . . . . . . . 95 11.5.1.2 relevant loadcon?g command error ?ags . . 96 11.5.2 calccrc command 12h . . . . . . . . . . . . . . . . . 96 11.5.2.1 crc coprocessor settings . . . . . . . . . . . . . . . 96 11.5.2.2 crc coprocessor status ?ags . . . . . . . . . . . . 96 11.6 error handling during command execution . . . 97 11.7 mifare security commands . . . . . . . . . . . . . 97 11.7.1 loadkeye2 command 0bh . . . . . . . . . . . . . . . 97 11.7.1.1 relevant loadkeye2 command error ?ags . . 97 11.7.2 loadkey command 19h . . . . . . . . . . . . . . . . . 97 11.7.2.1 relevant loadkey command error ?ags. . . . . 98 11.7.3 authent1 command 0ch . . . . . . . . . . . . . . . . . 98 11.7.4 authent2 command 14h . . . . . . . . . . . . . . . . . 98 11.7.4.1 authent2 command effects . . . . . . . . . . . . . . . 99 12 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 99 13 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.1 operating condition range . . . . . . . . . . . . . . . 99 13.2 current consumption . . . . . . . . . . . . . . . . . . 100 13.3 pin characteristics. . . . . . . . . . . . . . . . . . . . . 100 13.3.1 input pin characteristics . . . . . . . . . . . . . . . . 100 13.3.2 digital output pin characteristics . . . . . . . . . . 101 13.3.3 antenna driver output pin characteristics . . . 101 13.4 ac electrical characteristics . . . . . . . . . . . . . 102 13.4.1 separate read/write strobe bus timing . . . . . 102 13.4.2 common read/write strobe bus timing . . . . . 103 13.4.3 epp bus timing . . . . . . . . . . . . . . . . . . . . . . . 104 13.4.4 spi timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13.4.5 clock frequency . . . . . . . . . . . . . . . . . . . . . . 106 14 eeprom characteristics. . . . . . . . . . . . . . . . 107 15 application information . . . . . . . . . . . . . . . . 107 15.1 typical application . . . . . . . . . . . . . . . . . . . . 107 15.1.1 circuit diagram . . . . . . . . . . . . . . . . . . . . . . . 107 15.1.2 circuit description. . . . . . . . . . . . . . . . . . . . . 108 15.1.2.1 emc low-pass ?lter . . . . . . . . . . . . . . . . . . . 108 15.1.2.2 antenna matching . . . . . . . . . . . . . . . . . . . . 108 15.1.2.3 receiver circuit. . . . . . . . . . . . . . . . . . . . . . . 108 15.1.2.4 antenna coil . . . . . . . . . . . . . . . . . . . . . . . . . 109 15.2 test signals . . . . . . . . . . . . . . . . . . . . . . . . . 110 15.2.1 measurements using the serial signal switch 110 15.2.1.1 tx control. . . . . . . . . . . . . . . . . . . . . . . . . . . 110 15.2.1.2 rx control . . . . . . . . . . . . . . . . . . . . . . . . . . 111 15.2.2 analog test signals . . . . . . . . . . . . . . . . . . . . 112 15.2.3 digital test signals . . . . . . . . . . . . . . . . . . . . 113 15.2.4 examples of iso/iec 14443 a analog and digital test signals . . . . . . . . . . . . . . . . . 113 15.2.5 examples of i-code1 analog and digital test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16 package outline . . . . . . . . . . . . . . . . . . . . . . . 116 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 117 18 references . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 19 revision history . . . . . . . . . . . . . . . . . . . . . . 118 20 legal information . . . . . . . . . . . . . . . . . . . . . 119 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 119 20.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . 119 20.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 119 20.4 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 20.5 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 119 21 contact information . . . . . . . . . . . . . . . . . . . 120 22 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 23 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 24 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

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